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These are VHDL programs as per the JNTUH syllabus Given below:

NOT  GATE:-

VHDL CODE :

LIBRARY  IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

Entity not_1 is                                                               

port( a: in std_logic;

      y:out std_logic );                             

end not_1;

--DATA FLOW MODEL

Architecture behav1 of not_1 is

begin

y<=not  a;

end behav1;

---BEHAVIORAL MODEL

Architecture behav2 of not is

Begin

Process(a)

Begin

If(a=’0’)then    --compare with truth table

Y<=’0’;

End if;

End process;

End behav2;

NOT TEST BENCH RESULT:

NOT SIMULATION RESULT:

RESULT :

AND GATE:

VHDL CODE :

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

Entity and_2 is

port( a,b: in std_logic;

      y:out std_logic );

end and_2;

--DATA FLOW MODEL

Architecture behav1 of and_2 is

begin

y<= a and b;

end behav1;

---BEHAVIORAL MODEL

Architecture behav2 of AND2 is

Begin

Process(a,b)

Begin

If(a=’1’ and b=’1’)then --compare with truth table

Y<=’1’;

Else

Y<=’0’;

End if;

End process;

End behav2

AND TEST BENCH:

AND SIMULATION RESULT:

RESULT : 

NAND GATE

VHDL CODE :

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

Entity nand_2 is

port( a,b: in std_logic;

      y:out std_logic );

end nand_2;

--DATA FLOW MODEL

Architecture behav1 of nand_2 is

begin

y<= a nand b;

end behav1;

---BEHAVIORAL MODEL

Architecture behav2 of nand is

Begin

Process(a,b)

Begin

If(a=’1’ and b=’1’)then --compare with truth table

Y<=’0’;

Else

Y<=’1’;

End if;

End process;

End behav2

NAND TEST BENCH:

NAND SIMULATION RESULT:

RESULT:

OR GATE

VHDL CODE :

LIBRARY  IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

Entity or_2 is

port( a, b:in std_logic;

      y :out std_logic );

end or_2;

--DATAFLOW MODEL

Architecture behav1 of or_2 is

begin

y<= a or b;

end behav1;

---BEHAVIORAL MODEL

Architecture behav2 of or2 is

Begin

Process(a,b)

Begin

If(a=’0’ and b=’0’)then --compare with truth table

Y<=’0’;

Else

Y<=’1’;

End if;

End process;

End behav2

OR TEST BENCH:

OR SIMULATION RESULT:

RESULT:

XOR GATE:

VHDL CODE:

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

Entity xor_2 is

port( a,b: in std_logic;

      y:out std_logic );

end xor_2;

--DATA FLOW MODEL

Architecture behav1 of xor_2 is

begin

y<= a xor b;

end behav1;

---BEHAVIORAL MODEL

Architecture behav2 of xor2 is

Begin

Process(a,b)

Begin

If(a/=b)then      --compare with truth table

Y<=’1’;

Else

Y<=’0’;

End if;

End process;

End behav2

XOR TEST BENCH:

XOR SIMULATION RESULT:

RESULT: