Thursday 13 February 2014

techtgm - fingerprint protected anti theft tracking system, embedded project, M.Tech project














Introduction
Establishing the identity of a person is becoming critical in our vast interconnected society.  The need for reliable person authentication techniques has increased in the wake of high concerns about security and rapid advancement. Biometrics is described as the science of recognizing an individual based on physiological or behavioral traits. Biometrics has become popular over the traditional token based or knowledge based techniques (e.g. identification cards, passwords, PIN etc) This is because of the ability of biometrics technology to differentiate between an authorized person and imposter efficiently.
Generally if a vehicle lost and don’t know who has taken away the vehicle and where it is? In such situation, registering a complaint in police station and then investigation.. It is totally a risky and time consuming process and there is no guarantee of finding the vehicle. To overcome this problem and providing additional security, the proposed architecture will implement a small technique using GSM and GPS technologies with an additional future of biometric security.
Vehicle tracking systems are also popular in consumer vehicles as a theft prevention and retrieval device. Police can simply follow the signal emitted by the tracking system and locate the stolen vehicle. When used as a security system, a Vehicle Tracking System may serve as either an addition to or replacement for a traditional Car alarm. Some vehicle tracking systems make it possible to control vehicle remotely, including block doors or engine in case of emergency. The existence of vehicle tracking device then can be used to reduce the insurance cost.
1.1 Design implementation:
Design of this system includes Three parts, they are
i.            Interfacing
ii.          Coding
iii.        testing
     Here I am using three main modules those are fingerprint scanner, GPS module, GSM module and I have added vibration sensor, motor and its driver.
I assigned individual functionality to the individual modules to the individual modules. The Fingerprint module will store some person’s fingerprints by enrolling while the login has made. It will checks for authentication and compares fingerprints with stored data while login. GPS module will takes the latitude and longitude values and forwards its values to the controller. GSM module will communicate with controller and used for messaging by using ATL commands. Vibration sensor is used to detect accidents. Motor is used to verify the output. Here we can assume the motor as vehicle engine.
I interfaced all these modules after knowing their pin functionalities. I wrote coding by assigning their functionalities. Testing is done by seeing the exact values of GPS and at exact timings of out puts like fingerprint detection, motor starting/stopping etc.
1.2 Literature survey:
    This dissertation is to protect the vehicle by giving some advanced features than present system. Here I am giving security through fingerprint module. For developing this system we need to have the knowledge on the previous papers.
·           Ganesh, Balaji, Varadhan “Anti-Theft Tracking System for Automobiles” 2011  IEEE Paper
  •  Islam,  Karhu, Salonen” GPS and GSM antenna with a capacitive feed for a personal        avigator device”-IEEE Paper 2010
·         Cai-Cong Wu, Xiu-Wan Chen, Hong Li, Zhong-Zhong Wu, Ying-Chun Tao”Design and development of farm vehicle monitoring and intelligent dispatching system” 2004 IEEE paper.
·         Qiang Liu; Huapu Lu; Hongliang Zhang; Bo Zou “Research and Desing of Intelligent Vehicle Monitoring System Based on GPS/GSM” 2006 IEEE Paper.
  • Hindawi, Nader “Performance of differential GPS based on a real-time algorithm using SMS services of GSM network”  2012 IEEE Paper.
·         Peng Chen; Shuang Liu “Intelligent Vehicle Monitoring System, Based on GPS, GSM and GIS”  2010 IEEE Paper.
1.2.1 Anti-Theft Tracking System for Automobiles     
The working is simple and just similar to carrying a mobile phone along with you and connecting to it from another device. Here we vary the working from that of the GPS which connects through the internet and then a user interface, by just displaying the information containing the location and other essential details  through an SMS.
First, the GSM anti-theft tracking system is put to task when it receives a message from the user, which is during a vehicle hijack. This triggers the microcontroller in switching OFF the engine or it stimulates the module in forwarding the location or both.
1.2.2    GSM and GPS based vehicle location and tracking system    
This dissertation is designed using 8051 microcontroller in this dissertation it is proposed to design an embedded system which is used for tracking and positioning of any vehicle by using Global Positioning System (GPS) and Global system for mobile communication (GSM). In this project LPC2148 microcontroller is used for interfacing to various hardware peripherals. The current design is an embedded application, which will continuously monitor a moving Vehicle and report the status of the Vehicle on demand. For doing so an LPC2148 microcontroller is interfaced serially to a GSM Modem and GPS Receiver. A GSM modem is used to send the position (Latitude and Longitude) of the vehicle from a remote place. The GPS modem will continuously give the data i.e.  the latitude and longitude indicating the position of the vehicle. The GPS modem gives many parameters as the output, but only the NMEA data coming out is read and displayed on to the LCD. The same data is sent to the mobile at the other end from where the position of the vehicle is demanded. An EEPROM is used to store the mobile number. The hardware interfaces to microcontroller are LCD display, GSM modem and GPS Receiver. The design uses RS-232 protocol for serial communication between the modems and the microcontroller. A serial driver IC is used for converting TTL voltage levels to RS-232 voltage levels. In the main they are easy to steal, and the average motorist has very little knowledge of what it is all about. To avoid this kind of steal we are going to implement this project which provides more security to the vehicle. When the request by user is sent to the number at the modem, the system automatically sends a return reply to that mobile indicating the position of the vehicle in terms of latitude and longitude from this information we can track our vehicles.
1.2.3    Combining GPS and GSM Cell-ID positioning for Proactive Location-based Services                                                                                                                                     
Mobile terminals with built-in GPS receivers are becoming more and more available, thus the public deployment of location-based services (LBS) becomes feasible. Upcoming LBS are no longer only reactive but getting more and more proactive, enabling the users to subscribe for certain events and get notified when e.g. a friend approaches or a point of interest comes within proximity. However, power consumption for continuous tracking is still a major issue with mobile terminals. In this paper we define this problem and propose solutions for an energy efficient combination of GPS and GSM Cell-ID positioning for mobile terminals. We introduce    several strategies for extending the lifetime of the battery and show how these strategies can be integrated into existing middleware solutions. Simulations based on a realistic proactive multi-user context confirm the approach.
1.2.4    A New Approach of Automobile Localization System Using GPS and GSM/GPRS Transmission
This paper presents a low cost automotive localization system using GPS and GSM-SMS services. The system permits localization of the automobile and transmitting the position to the owner on his mobile phone as a short message (SMS) at his request. The system can be interconnected with the car alarm system and alert the owner, on his mobile phone, about the events that occurs with his car when it is parked. The system is composed by a GPS receiver, a microcontroller and a GSM phone. Additional, the system can be settled for acquiring and transmitting of information, when requested, about automobile status and parameters (engine status, speed, direction, etc.) or alert when it started engine, exceed a given speed limit or if leave a specific area. By using the PC connection, the system can be used as navigation system. Optional, the system can be used as car tracking system if connected with GSM/GPRS phone. The presented application is a low cost solution for automobile position localizing and status, very useful in case of car theft situations (alarm alert, engine starting, localizing), for adolescent drivers watching and monitoring by their parents (speed limit exceeding, leaving a specific area), as well as in car tracking system application. The proposed solution can be used in other types of application, where the information needed are requested rarely and at irregular period of time (when requested).
1.2.5    Research and Design of Intelligent Vehicle Monitoring System Based on GPS/GSM
Based on the principle of the intelligent vehicle monitoring system using GPS/GSM, this paper analyzed the key technologies of the system such as GIS, wireless positioning and communication. Details about the design and implementation of the system are discussed in this paper. Such a system provides practical measures to resolve problems like vehicle hijacking and theft in traffic control and management. In addition, this system also offers certain references in monitoring civil vehicles and providing cogent evidence for vehicle theft cases
1.2.6    Design and development of farm vehicle monitoring and intelligent dispatching system

More and more large farms adopt precision agriculture technology in China. On the base of requirement investigation, the paper designed and developed farm vehicle monitoring and intelligent dispatching system (FVMIDS) for a large farm, which owns 13,000 hm2 of land and has the most advanced agricultural mechanism in the world. The principle, technology and method of GPS, GIS, GSM and operational research were used for system design and development. The system could meet the following requirements: vehicle dispatching, vehicle inducing, vehicle monitoring, farming operation analyzing & statistics, means of production dispatching, and so on. The model of vehicle dispatching based on "transportation problem" was emphasized in the paper. Test run shows that the system can meet all the requirements of the farm and decrease vehicle-dispatching cost largely.
1.2.2    Intelligent Vehicle Monitoring System Based on GPS, GSM and GIS
To meet the requirements of some intelligent vehicle monitoring system, the software integrates Global Position System (GPS), Geographic Information System (GIS) and Global System for Mobile communications (GSM) in the whole. The structure, network topology, functions, main technical features and their implementation principles of the system are introduced. Then hardware design of the vehicle terminal is given in short. Communication process and data transmission between the server and the client (relay server) and client through TCP/IP and UDP protocol are discussed in detail in this paper. Testing result using LoadRunner software is also analyzed. Practice shows the robustness of the software and feasibility of object-oriented programming.
1.2.3    GPS and GSM antenna with a capacitive feed for a personal navigator device:
In this paper, the GPS and GSM antenna system with the new capacitive feed for a personal navigator is proposed. A very simple and effective antenna solution is introduced, making use of the device back cover in the antenna design. Compact size and good performance make this antenna an attractive solution for a personal navigator device. The antenna is capable for wide band GPS and forur-band GSM coverage.
1.2.4    Required Knowledge for the project Implementation:
·         Embedded C programming
·         Different Microcontrollers and specifications.
·         Interfacing techniques for microcontroller with GSM, GPS, fingerprint, vibration sensor and motor.
·         Detailed knowledge on GSM, GPS, fingerprint modules.
·         Knowledge on Keil, Proteus, Flash magic softwares.


CHAPTER 2
Microcontroller

2.1 Introduction to Microcontroller:

A microprocessor system consists of a microprocessor with memory, input ports and output ports connected to it externally. A microcontroller is a single chip containing a microprocessor, memory, input ports and output ports. Since all four blocks reside on the one chip, a microcontroller is much faster than a microprocessor system.                 
We have several other basic microcontroller families such as PIC, M68HCXX, and AVR etc. All these basic microcontrollers are useful for implementing basic interfacing and control mechanisms for simple applications. There are several applications which require lot of computation and high speed data processing. In such applications advanced microcontrollers and microprocessors are used. One such advanced architecture is ARM.

2.2 History of ARM:

ARM stands for Advanced RISC machine. The first processor in ARM family was developed at Acorn Computers Ltd between October 1983 and April 1985. Acorn Computers was a British computer company established in Cambridge, England, in 1978. The company worked for Reduced Instruction Set Computer (RISC) processor design. The company produced a variety of computers which were very popular in the United Kingdom. These included the Acorn Electron, the BBC Micro and the Acorn Archimedes. Particularly BBC Micro computer dominated the UK educational computer market during the 1980s and early 1990s.

2.3 ARM Architecture:

The ARM core uses RISC architecture. Its design philosophy is aimed at delivering simple but powerful instructions that execute within a single cycle at a high clock speed. The RISC philosophy concentrates on reducing the complexity of instructions performed by the hardware because it is easier to provide greater flexibility and intelligence in software rather than hardware. As, a result RISC design plays greater demands on the compiler. In contrast, the traditional complex instruction set computer (CISC) relies more on the hardware for instruction functionality, AND consequently the CISC instructions are more complicated. Certain design features have been characteristic of most RISC processors:
One cycle execution time: RISC processors have a CPI (clock per instruction) of one cycle. This is due to the optimization of each instruction on the CPU. Each instruction is of a fixed length to allow the pipeline to fetch future instructions before decoding the current instruction.
Pipelining:  The processing of instructions is broken down into smaller units that can be executed in parallel by pipelines. Ideally the pipeline advances by one step on each cycle for maximum throughput. Instructions can be decoded in one pipeline stage.
Large number of registers: The RISC design philosophy generally incorporates a larger number of registers to prevent large amount of interactions with memory. Any register can contain either data or an address. Registers act as the fast local memory store for all data processing operation.
Load-store architecture: The processor operates on data held in registers. Separate load and store instructions transfer data between the register bank and external memory
These design rules allow a RISC processor to be simpler, and thus the core can operate at higher clock frequencies.

2.4 ARM Processor Core:

Similar to most RISC machines ARM works on load-store architecture, so only load and store instructions perform memory operations and all other arithmetic and logical operations are only performed on processor registers. The figure shows the ARM core data flow model. In which the ARM core as functional units connected by data buses,. And the arrows represent the flow of data, the lines represent the buses, and boxes represent either an operation unit or a storage area. The figure shows not only the flow of data but also the abstract components that make up an ARM core.
In the above figure the Data enters the processor core through the Data bus. The data may be an instruction to execute or a data item. This ARM core represents the Von Neumann implementation of the ARM data items and instructions share the same bus. In contrast, Harvard implementations of the ARM use two different buses.
The instruction decoder translates instructions before they are executed. Each instruction executed belongs to a particular instruction set.
The ARM processors, like all RISC processors, use load-store architecture. This means it has two instruction types for transferring data in and out of the processor: load instructions copy data from memory to registers in the core, and conversely the store instructions copy data from registers to memory. There are no data processing instructions that directly manipulate data in memory. Thus, data processing is carried out solely in registers.
Data items are placed in the register file – a storage bank made up of 32-bit registers. Since the ARM core is a 32- bit processor, most instructions treat the registers as holding signed or unsigned 32-bit values. The sign extend hardware converts signed 8-bit and 16-bit numbers to 32-bit values as they are read from memory and placed in a register.
The ALU (arithmetic logic unit) or MAC (multiply – accumulate unit) takes the register values Rn and Rm from the A and B buses and computes a result. Data processing instructions write the result in Rd directly to the register file. Load and store instructions use the ALU to generate an address to be held in the address register and broadcast on the Address bus.
One important feature of the ARM is that register Rm alternatively can be preprocessed in the barrel shifter before it enters the ALU. Together the barrel shifter and ALU can calculate a wide range of expressions and addresses.
After passing through the functional units, the result in Rd is written back to the register file using the Result bus. For load and store instructions the incrementer updates the address register before the core reads or writes the next register value from or to the next sequential memory location. The processor continues executing instructions until an exception or interrupt changes the normal execution flow.

2.4.1 ARM Bus Technology:

Embedded systems use different bus technologies. The Peripheral Component Interconnect (PCI) bus connects devices such as video card and disk controllers to the X 86 processor buses. This is called External or off chip bus technology.
Embedded devices use an on-chip bus that is internal to the chip and allows different peripheral devices to be inter-connected with an ARM core.
There are two different types of devices connected to the bus
1.                  Bus Master
2.                  Bus Slave
Bus Master: A logical device capable of initiating a data transfer with another device across the same bus (ARM processor core is a bus Master).
Bus Slave: A logical device capable only of responding to a transfer request from a bus master device (Peripherals are bus slaves)
Generally a Bus has two architecture levels
 Physical lever: Which covers electrical characteristics a bus width (16, 32, 64 bus).
 Protocol level: which deals with protocol?
NOTE: - ARM is primarily a design company. It seldom implements the electrical characteristics of the bus, but it routinely specifies the bus protocol

2.4.2 AMBA (Advanced Microcontroller Bus Architecture) Bus protocol:

AMBA Bus was introduced in 1996 and has been widely adopted as the On Chip bus architecture used for ARM processors.
The first AMBA buses were
1.                  ARM System Bus ( ASB )
2.                  ARM Peripheral Bus ( APB )
Later ARM introduced another bus design called the ARM High performance Bus (AHB).
Using AMBA
i.                    Peripheral designers can reuse the same design on multiple projects
ii.                  A Peripheral can simply be bolted on the On Chip bus with out having to redesign an interface for different processor architecture.
This plug-and-play interface for hardware developers improves availability and time to market.
AHB provides higher data throughput than ASB because it is based on centralized multiplexed bus scheme rather than the ASB bidirectional bus design. This change allows the AHB bus to run at widths of 64 bits and 128 bits
ARM introduced two variations on the AHB bus
1.                  Multi-layer AHB
2.                  AHB-Lite
In contrast to the original AHB , which allows a single bus master to be active on the bus at any time , the Multi-layer AHB bus allows multiple active bus masters.
AHB-Lite is a subset of the AHB bus and it is limited to a single bus master. This bus was developed for designs that do not require the full features of the standard AHB bus.
AHB and Multiple-layer AHB support the same protocol for master and slave but have different interconnects. The new interconnects in Multi-layer AHB are good for systems with multiple processors. They permit operations to occur in parallel and allow for higher throughput rates.

2.4.3 ARCHITECTURE Revisions:

Every ARM processor implementation executes a specific instruction set architecture (ISA), although an ISA revision may have more than one processor implementation .The ISA has evolved to keep up with the demands of the embedded market. This evolution has been carefully managed by ARM, so that code written to execute on an earlier architecture revision will also execute on a later revision of the architecture. The nomenclature identifies individual processors and provides basic information about the feature set.

2.4.4 NOMENCLATURE:

ARM uses the nomenclature shown below is to describe the processor implementations. The letters and numbers after the word “ARM” indicate the features a processor may have.
 ARM { x }{ y }{ z }{ T }{ D }{ M }{ I }{ E }{J }{ F }{ -S }
  x → family
  y → memory management / protection unit
 z → cache
 T → Thumb 16 bit decoder
 D → JTAG debug
 M → fast multiplier
 I → Embedded ICE macro cell
 E → enhanced instruction (assumes TDMI)
 J → Jazelle
 F → vector floating-point unit
 S → synthesizable version
Ø  All ARM cores after the ARM7TDMI include the TDMI features even though they may not include those letters after the “ ARM ” label
Ø  The processor family is a group of processor implementations that share the same hardware characteristics. For example, the ARM7TDMI, ARM740T, and ARM720T all share the same family characteristics and belong to the ARM7 family
Ø  JTAG is described by IEEE 1149.1 standard Test Access Port and boundary scan architecture. It is a serial protocol used by ARM to send and receive debug information between the processor core and test equipment
Ø  Embedded ICE macro cell is the debug hardware built into the processor that allows breakpoints and watch points to be set
Ø  Synthesizable means that the processor core is supplied as source code that can be compiled into a form easily used by EDA  tools.

2.4.5 Introduction to ARM7TDMI core:

The ARM7TDMI core is a 32-bit embedded RISC processor delivered as a hard macro cell optimized to provide the best combination of performance, power and area characteristics.

2.4.6 ARM7TDMI Features:

1)      32/16-bit RISC architecture (ARM v4T)
2)      32-bit ARM instruction set for maximum performance and flexibility
3)      16-bit Thumb instruction set for increased code density
4)      Unified bus interface, 32-bit data bus carries both instructions and data
5)      Three-stage pipeline
6)      32-bit ALU
7)      Very small die size and low power consumption
8)      Fully static operation
9)      Coprocessor interface
10)  Extensive debug facilities (Embedded ICE debug unit accessible via JTAG interface unit)

2.4.7 Benefits:

1)      Generic layout can be ported to specific process technologies
2)      Unified memory bus simplifies SoC integration process
3)      ARM and Thumb instructions sets can be mixed with minimal overhead to support application requirements for speed and code density
4)      Code written for ARM7TDMI-S is binary-compatible with other members of the ARM7 Family and forwards compatible with ARM9, ARM9E and ARM10 families, thus it's quite easy to port your design to higher level microcontroller or microprocessor
5)      Static design and lower power consumption are essential for battery -powered devices
6)      Instruction set can be extended for specific requirements using coprocessors
7)      Embedded ICE-RT and optional ETM units enable extensive, real-time debug facilities

2.5 ARM Register file & modes of operation:

The ARM architecture has register file with 37 registers. In addition to these registers there will be several other registers inside the processor which will not be visible to the programmer but used by the processor internally to execute instructions. The current program status register (CPSR) has condition flags and several other control bits. When the ARM enters in privileged modes it has access to some special registers as explained below.
However these are arranged into several banks, with the accessible bank being governed by the processor mode. Each mode can access a particular set of r0-r12 registers, a particular r13 (the stack pointer) and r14 (link register), r15 (the program counter), cpsr (the current program status register)and privileged modes can also access a particular spsr (saved program status register).In user mode 16 data registers and 2 status registers are visible. Depending upon context, register r13 and r14 can also be used as General Purpose Registers. In ARM state the registers r0 to r13 are Orthogonal that means - any instruction which use r0 can as well be used with any other General Purpose Register (r1-r13).
1)        The ARM processor has three registers assigned to a particular task or special function: r13, r14 and r15. They are frequently given different labels to differentiate them from the other registers.
2)        Register r13 is traditionally used as the stack pointer (sp) and stores the head of the stack in the current processor mode
3)        Register r14 is called the link register (lr) and is where the core puts the return address whenever it calls a subroutine.
4)        Register r15  is the program counter ( pc ) and contains the address of the next instruction to be fetched by the processor
5)        The register file contains all the registers available to a programmer. Which registers are visible to the programmer depend upon the current mode of the processor.

2.5.1 ARM Modes of Operation:

ARM has total seven modes of operation. They are user , abort, fast interrupt, request, interrupt request, supervisor, system and undefined. Out of all these modes the user mode is non-privileged mode which does not have write permissions to CPSR. The other six modes are privileged modes.
Privileged: - Full read-write access to the CPSR. Under this we are having Abort, Fast interrupt request, Interrupt request, Supervisor, System and Undefined.
Abort (10111): When there is a failed attempt to access memory
Fast interrupt Request (FIQ (10001)) & interrupt request (10010) : Correspond to interrupt levels available on ARM  
Supervisor mode (10011): State after reset and generally the mode in which OS kernel executes
System mode (11111): Special version of user mode that allows full read-write access of CPSR.
Undefined (11011): When processor encounters an undefined instruction
Non-privileged:- Only read access to the control filed of CPSR but read-write access to the condition flags.
User (10000): User mode is user for programs and applications. And this is the normal mode

The above figure shows all 37 registers of register file. Out of these 37 registers, 20 registers are hidden from a program in different modes. These are called banked registers

2.5.2 Current program status registers:

The CPSR is a 32 bit register in addition to the 16 general purpose registers. The CPSR has flag and control bits in it. The following figure illustrates the bit positions of various control or flag bits of CPSR.
The CPSR is divided into 4 fields, each of 8 bits size. They are Flag, status, extension and control fields. In the present versions of ARM the status and extensions field’s bits are reserved for future use.
If flag up date option is enabled1 then the flag bits will be changed as described below. Remember that flag bits are only affected when such option is chosen in the instruction; otherwise flag bits will preserve their old values.
N – Negative flag; this bit is set when the 31 bit (most significant bit) of result is one, otherwise it is reset
Z – Zero flag; this bit set if the result is zero, otherwise it is reset
C – carry flag; this bit is set when there is a carry out of addition and no barrow for subtraction, otherwise it is reset
V – overflow flag; this bit is set when there is overflow in signed arithmetic operations
The I and F bits correspond to interrupt masking and the T bit tells the thumb state (whether the processor is in normal mode or thumb mode).
The least significant five bits of CPSR indicate the mode in which processor is currently operating. Except in user mode in all other modes it is possible to write appropriate value in these bits for changing to any other mode. The mode also can be changed when exception or interrupt occurs. The following exceptions and interrupts results in mode change: reset, interrupt request, and fast interrupt request, software interrupt, data abort, pre-fetch abort and execution of undefined instruction.

2.5.3 Banked registers:

Out of total 37 registers in register file at any time the processor accesses 17 registers, remaining 20 registers are called banked registers. If the processor is in user mode it accesses all R0 to R15 and CPSR register which are shown in first column in above diagram. Banked registers are available only when the processor is in a particular mode. Processor modes (other than system mode) have a set of associated banked registers that are subset of 16 register.
Consider if the processor is in fast interrupt request mode then the register R8_fiq is used instead of R8 and similarly for few other registers as shown in above figure. So the original R8 register is unchanged when the processor comes back to the user mode.

2.5.4 SPSR:

The saved program status registers (SPSR) stores the previous mode’s CPSR when there is a mode change. When the processor returns by using special return instruction the CPSR is restored from the corresponding SPSR. Each privileged mode (except system mode) has associated with it a Save Program Status Register, or SPSR.
Mode Changing:
Mode changes by writing directly to CPSR or by hardware when the processor responds to exception or interrupt.
To return to user mode a special return instruction is used that instructs the core to restore the original CPSR and banked registers.

2.6 ARM Instruction Set:

Different ARM architectures revisions support different instructions. However new revisions usually add instructions and remain backwardly compatible. The following shows the type of instructions that ARM support.
I.                      Data Processing Instructions
II.                   Branch Instructions
III.                Load-store Instructions
IV.                Software Interrupt Instruction
V.                 Program Status Register Instructions 


CHAPTER 3

LPC2148 MICROCONTROLLER

3.3.1 General description
The LPC2141/42/44/46/48 microcontrollers are based on a 16-bit/32-bit ARM7TDMI-S CPU with real-time emulation and embedded trace support, that combine the microcontroller with embedded high-speed flash memory ranging from 32 kB to 512 kB. A 128-bit wide memory interface and a unique accelerator architecture enable 32-bit code execution at the maximum clock rate. For critical code size applications, the alternative 16-bit Thumb mode reduces code by more than 30 % with minimal performance penalty. Due to their tiny size and low power consumption, LPC2141/42/44/46/48 are ideal for applications where miniaturization is a key requirement, such as access control and point-of-sale. Serial communications interfaces ranging from a USB 2.0 Full-speed device, multiple UARTs, SPI, SSP to I2C-bus and on-chip SRAM of 8 kB up to 40 kB, make these devices very well suited for communication gateways and protocol converters, soft modems, voice recognition and low end imaging, providing both large buffer size and high processing power. Various 32-bit timers, single or dual 10-bit ADC(s), 10-bit DAC, PWM channels and 45 fast GPIO lines with up to nine edge or level sensitive external interrupt pins make these microcontrollers suitable for industrial control and medical systems.
2.3.2 Features and benefits
2.3.2.1 Key features
·         16-bit/32-bit ARM7TDMI-S microcontroller in a tiny LQFP64 package.
·         8 kB to 40 kB of on-chip static RAM and 32 kB to 512 kB of on-chip flash memory.
·         128-bit wide interface/accelerator enables high-speed 60 MHz operation.
·         In-System Programming/In-Application Programming (ISP/IAP) via on-chip boot
loader software. Single flash sector or full chip erase in 400 ms and programming of
256 B in 1 ms.
·         EmbeddedICE RT and Embedded Trace interfaces offer real-time debugging with the
on-chip RealMonitor software and high-speed tracing of instruction execution.
·         USB 2.0 Full-speed compliant device controller with 2 kB of endpoint RAM.In addition, the LPC2146/48 provides 8 kB of on-chip RAM accessible to USB by DMA.
·         One or two (LPC2141/42 vs. LPC2144/46/48) 10-bit ADCs provide a total of 6/14 analog inputs, with conversion times as low as 2.44 s per channel.
·         Single 10-bit DAC provides variable analog output (LPC2142/44/46/48 only).
·         Two 32-bit timers/external event counters (with four capture and four compare channels each), PWM unit (six outputs) and watchdog.
·         Low power Real-Time Clock (RTC) with independent power and 32 kHz clock input.
·         Multiple serial interfaces including two UARTs (16C550), two Fast I2C-bus (400 kbit/s),
SPI and SSP with buffering and variable data length capabilities.
·         Vectored Interrupt Controller (VIC) with configurable priorities and vector addresses.
·         Up to 45 of 5 V tolerant fast general purpose I/O pins in a tiny LQFP64 package.
·         Up to 21 external interrupt pins available.
·         60 MHz maximum CPU clock available from programmable on-chip PLL with settling
time of 100 s.
·         On-chip integrated oscillator operates with an external crystal from 1 MHz to 25 MHz.
·         Power saving modes include Idle and Power-down.
·         Individual enable/disable of peripheral functions as well as peripheral clock scaling for
additional power optimization.
·         Processor wake-up from Power-down mode via external interrupt or BOD.
·         Single power supply chip with POR and BOD circuits:

·         CPU operating voltage range of 3.0 V to 3.6 V (3.3 V 10 %) with 5 V tolerant I/O pads.
 While the USB DMA is the primary user of the additional 8 kB RAM, this RAM is also accessible at any time by the CPU as a general purpose RAM for data and code storage.
2.4. Block diagram of micro controller








2.5 Pinning information

3.6 Functional description
3.6.1 Architectural overview
     The ARM7TDMI-S is a general purpose 32-bit microprocessor, which offers high performance and very low power consumption. The ARM architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and related decode mechanism are much simpler than those of  microprogrammed Complex Instruction Set Computers (CISC). This simplicity results in a high instruction throughput and impressive real-time interrupt response from a small and cost-effective processor core.
Pipeline techniques are employed so that all parts of the processing and memory systems can operate continuously. Typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory. The ARM7TDMI-S processor also employs a unique  architectural strategy known as Thumb, which makes it ideally suited to high-volume applications with memory restrictions, or applications where code density is an issue. The key idea behind Thumb is that of a super-reduced instruction set. Essentially, the ARM7TDMI-S processor has two instruction sets:
The standard 32-bit ARM set.
A 16-bit Thumb set.
     The Thumb set’s 16-bit instruction length allows it to approach twice the density of standard ARM code while retaining most of the ARM’s performance advantage over a traditional 16-bit processor using 16-bit registers. This is possible because Thumb code operates on the same 32-bit register set as ARM code.
     Thumb code is able to provide up to 65 % of the code size of ARM, and 160 % of the performance of an equivalent ARM processor connected to a 16-bit memory system. The particular flash implementation in the LPC2141/42/44/46/48 allows for full speed execution also in ARM mode. It is recommended to  program performance critical and short code sections (such as interrupt service routines and DSP algorithms) in ARM mode. The impact on the overall code size will be minimal but the speed can be increased by 30 % over Thumb mode.
3.6.2 On-chip flash program memory
     The LPC2141/42/44/46/48 incorporate a 32 kB, 64 kB, 128 kB, 256 kB and 512 kB flash memory system respectively. This memory may be used for both code and data storage. Programming of the flash memory may be accomplished in several ways. It may be programmed In System via the serial port. The application program may also erase and/or program the flash while the application is running, allowing a great degree of flexibility for data storage field firmware upgrades, etc. Due to the architectural solution chosen for an on-chip boot loader, flash memory available for user’s code on LPC2141/42/44/46/48 is 32 kB, 64 kB, 128 kB, 256 kB and 500 kB respectively. The LPC2141/42/44/46/48 flash memory provides a minimum of 100000 erase/write cycles and 20 years of data-retention.
3.6.3 On-chip static RAM
     On-chip static RAM may be used for code and/or data storage. The SRAM may be accessed as 8-bit, 16-bit, and 32-bit. The LPC2141, LPC2142/44 and LPC2146/48 provide 8 kB, 16 kB and 32 kB of static RAM respectively. In case of LPC2146/48 only, an 8 kB SRAM block intended to be utilized mainly by the USB can also be used as a general purpose RAM for data storage and code storage and execution.
3.6.4 Memory map
     The LPC2141/42/44/46/48 memory map incorporates several distinct regions,In addition, the CPU interrupt vectors may be remapped to allow them to reside in either flash memory (the default) or on-chip static RAM.


3.6.5 Interrupt controller
     The Vectored Interrupt Controller (VIC) accepts all of the interrupt request inputs and categorizes them as Fast Interrupt request (FIQ), vectored Interrupt Request (IRQ), and non-vectored IRQ as defined by programmable settings. The programmable assignment scheme means that priorities of interrupts from the various peripherals can be dynamically assigned and adjusted. FIQ has the highest priority. If more than one request is assigned to FIQ, the VIC combines the requests to produce the FIQ signal to the ARM processor. The fastest possible FIQ latency is achieved when only one request is classified as FIQ, because then the FIQ service routine does not need to branch into the interrupt service routine but can run from the interrupt vector location. If more than one request is assigned to the FIQ class, the FIQ service routine will read a word from the VIC that identifies which FIQ source(s) is (are) requesting an interrupt. Vectored IRQs have the middle priority. Sixteen of the interrupt requests can be assigned to this category. Any of the interrupt requests can be assigned to any of the 16 vectored IRQ slots, among which slot 0 has the highest priority and slot 15 has the lowest. Non-vectored IRQs have the lowest priority. The VIC combines the requests from all the vectored and non-vectored IRQs to produce the IRQ signal to the ARM processor. The IRQ service routine can start by reading a register from the VIC and jumping there. If any of the vectored IRQs are pending, the VIC provides the address of the highest-priority requesting  IRQs service routine, otherwise it provides the address of a default routine that is shared by all the non-vectored IRQs. The default routine can read another VIC register to see what IRQs are active.
3.6.5.1 Interrupt sources
     Each peripheral device has one interrupt line connected to the Vectored Interrupt Controller, but may have several internal interrupt flags. Individual interrupt flags may also represent more than one interrupt source.
3.6.6 Pin connect block
     The pin connect block allows selected pins of the microcontroller to have more than one function. Configuration registers control the multiplexers to allow connection between the pin and the on chip peripherals. Peripherals should be connected to the appropriate pins prior to being activated, and prior to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is not mapped to a related pin should be considered undefined. The Pin Control Module with its pin select registers defines the functionality of the microcontroller in a given hardware environment. After reset all pins of Port 0 and Port 1 are configured as input with the following exceptions: If debug is enabled, the JTAG pins will  assume their JTAG functionality; if trace is enabled, the Trace pins will assume their trace functionality. The pins associated with the I2C0 and I2C1 interface are open drain.
3.6.7 Fast general purpose parallel I/O (GPIO)
     Device pins that are not connected to a specific peripheral function are controlled by the GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate registers allow setting or clearing any number of outputs simultaneously. The value of the output register may be read back, as well as the current state of the port pins. PC2141/42/44/46/48 introduced accelerated GPIO functions over prior LPC2000 devices:
GPIO registers are relocated to the ARM local bus for the fastest possible I/O timing.
Mask registers allow treating sets of port bits as a group, leaving other bits unchanged.
All GPIO registers are byte addressable.
Entire port value can be written in one instruction.
3.6.7 Features
Bit-level set and clear registers allow a single instruction set or clear of any number of bits in one port.
Direction control of individual bits.
Separate control of output set and clear.
All I/O default to inputs after reset.
3.6.8 10-bit ADC
The LPC2141/42 contains one and the LPC2144/46/48 contain two analog to digital converters. These converters are single 10-bit successive approximation analog to digital converters. While ADC0 has six channels, ADC1 has eight channels. Therefore, total number of available ADC inputs for LPC2141/42 is 6 and for LPC2144/46/48 is 14.
3.6.8.1 Features
10 bit successive approximation analog to digital converter.
Measurement range of 0 V to VREF (2.5 V VREF VDDA).
Each converter capable of performing more than 400000 10-bit samples per second.
Every analog input has a dedicated result register to reduce interrupt overhead.
Burst conversion mode for single or multiple inputs.
Optional conversion on transition on input pin or timer match signal.
Global Start command for both converters (LPC2142/44/46/48 only).
3.6.9 10-bit DAC
The DAC enables the LPC2141/42/44/46/48 to generate a variable analog output. The maximum DAC output voltage is the VREF voltage.
3.6.9.1 Features
10-bit DAC.
Buffered output.
Power-down mode available.
3.6.10 USB 2.0 device controller
The USB is a 4-wire serial bus that supports communication between a host and a number (127 max) of peripherals. The host controller allocates the USB bandwidth to attached devices through a token based protocol. The bus supports hot plugging, unplugging, and dynamic configuration of the devices. All transactions are initiated by the host controller. The LPC2141/42/44/46/48 is equipped with a USB device controller that enables 12 Mbit/s data exchange with a USB host controller. It consists of a register interface, serial interface engine, endpoint buffer memory and DMA controller. The serial interface engine decodes the USB data stream and writes data to the appropriate end point buffer memory. The status of a completed USB transfer or error condition is indicated via status registers. An interrupt is also generated if enabled. A DMA controller (available in LPC2146/48 only) can transfer data between an endpoint buffer and the USB RAM.


3.6.10.1 Features
Fully compliant with USB 2.0 Full-speed specification.
Supports 32 physical (16 logical) endpoints.
Supports control, bulk, interrupt and isochronous endpoints.
Scalable realization of endpoints at run time.
Endpoint maximum packet size selection (up to USB maximum specification) by
software at run time.
RAM message buffer size based on endpoint realization and maximum packet size.
Supports Soft Connect and Good Link LED indicator. These two functions are sharing
one pin.
Supports bus-powered capability with low suspend current.
Supports DMA transfer on all non-control endpoints (LPC2146/48 only).
One duplex DMA channel serves all endpoints (LPC2146/48 only).
Allows dynamic switching between CPU controlled and DMA modes (only in
LPC2146/48).
Double buffer implementation for bulk and isochronous endpoints.
3.6.11 UARTs
The LPC2141/42/44/46/48 each contain two UARTs. In addition to standard transmit and receive data lines, the LPC2144/46/48 UART1 also provides a full modem control handshake interface. Compared to previous LPC2000 microcontrollers, UARTs in LPC2141/42/44/46/48 introduce a fractional baudrate generator for both UARTs, enabling these microcontrollers to achieve standard baud rates such as  115200 with any crystal frequency above 2 MHz. In addition, auto-CTS/RTS flow-control functions are fully implemented in hardware (UART1 in LPC2144/46/48 only).
3.6.11.1 Features
16 B Receive and Transmit FIFOs.
Register locations conform to 16C550 industry standard.
Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B
Built-in fractional baud rate generator covering wide range of baud rates without a need for external crystals of particular values.
Transmission FIFO control enables implementation of software (XON/XOFF) flow control on both UARTs.
LPC2144/46/48 UART1 equipped with standard modem interface signals. This module also provides full support for hardware flow control (auto-CTS/RTS).
3.6.12 I2C-bus serial I/O controller
The LPC2141/42/44/46/48 each contain two I2C-bus controllers. The I2C-bus is bidirectional, for inter-IC control using only two wires: a Serial Clock Line (SCL), and a Serial DAta line (SDA). Each device is  recognized by a unique address and can operate as either a receiver-only device (e.g., an LCD driver or a transmitter with the capability to both receive and send information (such as memory)). Transmitters and/or receivers can operate in either master or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed. The I2C-bus is a multi-master bus, it can be controlled by more than one bus master connected to it. The I2C-bus implemented in LPC2141/42/44/46/48 supports bit rates up to 400 kbit/s (Fast I2C-bus).


3.6.12.1 Features
Compliant with standard I2C-bus interface.
Easy to configure as master, slave, or master/slave.
Programmable clocks allow versatile rate control.
Bidirectional data transfer between masters and slaves.
Multi-master bus (no central master).
Arbitration between simultaneously transmitting masters without corruption of serial data on the bus.
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer.
The I2C-bus can be used for test and diagnostic purposes.
3.6.13 SPI serial I/O controller
The LPC2141/42/44/46/48 each contain one SPI controller. The SPI is a full duplex serial interface, designed to handle multiple masters and slaves connected to a given bus. Only a single master and a single slave can communicate on the interface during a given data transfer. During a data transfer the master always sends a byte of data to the slave, and the slave always sends a byte of data to the master.
3.6.13.1 Features
Compliant with SPI specification.
Synchronous, Serial, Full Duplex, Communication.
Combined SPI master and slave.
Maximum data bit rate of one eighth of the input clock rate.
3.6.14 SSP serial I/O controller
The LPC2141/42/44/46/48 each contain one Serial Synchronous Port controller (SSP). The SSP controller is capable of operation on a SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the bus. However, only a single master and a single slave can communicate on the bus during a given data transfer. The SSP supports full duplex transfers, with data frames of 4 bits to 16 bits of data flowing from the master to the slave and from the slave to the master. Often only one of these data flows carries meaningful data.
3.6.14.1 Features
Compatible with Motorola’s SPI, TI’s 4-wire SSI and National Semiconductor’s Microwire buses.
Synchronous serial communication.
Master or slave operation.
8-frame FIFOs for both transmit and receive.
Four bits to 16 bits per frame.
3.6.15 General purpose timers/external event counters
The Timer/Counter is designed to count cycles of the peripheral clock (PCLK) or an externally supplied clock and optionally generate interrupts or perform other actions at  specified timer values, based on four match registers. It also includes four capture inputs to trap the timer value when an input signal transitions, optionally generating an interrupt. Multiple pins can be selected to perform a single capture or match function, providing an application with ‘or’ and ‘and’, as well as ‘broadcast’ functions among them.
The LPC2141/42/44/46/48 can count external events on one of the capture inputs if the minimum external pulse is equal or longer than a period of the PCLK. In this configuration, unused capture lines can be  selected as regular timer capture inputs, or used as external interrupts.
3.6.15.1 Features
1)      A 32-bit timer/counter with a programmable 32-bit prescaler.
2)      External event counter or timer operation.
3)      Four 32-bit capture channels per timer/counter that can take a snapshot of the timer value when an input signal transitions. A capture event may also optionally generate an interrupt.
4)      Four 32-bit match registers that allow:
a)                  Continuous operation with optional interrupt generation on match.
b)                  Stop timer on match with optional interrupt generation.
c)                  Reset timer on match with optional interrupt generation.
5)      Four external outputs per timer/counter corresponding to match registers, with the following capabilities:
a)                  Set LOW on match.
b)                  Set HIGH on match.
c)                  Toggle on match.
d)                 Do nothing on match.
3.6.16 Watchdog timer
The purpose of the watchdog is to reset the microcontroller within a reasonable amount of time if it enters an erroneous state. When enabled, the watchdog will generate a system reset if the user program fails to ‘feed’ (or reload) the watchdog within a predetermined amount of time.

3.6.16.1 Features
1)      Internally resets chip if not periodically reloaded.
2)      Debug mode.
3)      Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be disabled.
4)      Incorrect/Incomplete feed sequence causes reset/interrupt if enabled.
5)      Flag to indicate watchdog reset.
6)      Programmable 32-bit timer with internal pre-scaler.
3.6.17 Real-time clock
The RTC is designed to provide a set of counters to measure time when normal or idle operating mode is selected. The RTC has been designed to use little power, making it suitable for battery powered systems where the CPU is not running continuously (Idle mode).
3.6.17.1 Features
1)      Measures the passage of time to maintain a calendar and clock.
2)      Ultra-low power design to support battery powered systems.
3)      Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and Day of Year.
4)      Can use either the RTC dedicated 32 kHz oscillator input or clock derived from the external crystal/oscillator input at XTAL1. Programmable reference clock divider allows fine adjustment of the RTC.
5)      Dedicated power supply pin can be connected to a battery or the main 3.3 V.

3.6.18 Pulse width modulator
The PWM is based on the standard timer block and inherits all of its features, although only the PWM function is pinned out on the LPC2141/42/44/46/48. The timer is designed to count cycles of the  eripheral clock (PCLK) and optionally generate interrupts or perform other actions when specified timer values  occur, based on seven match registers. The PWM function is also based on match register events. The ability to separately control rising and falling edge locations allows the PWM to be used for more applications. For instance, multi-phase motor control typically requires three non-overlapping PWM outputs with individual control of all three pulse widths and positions. Two match registers can be used to provide a single edge controlled PWM output. One match register (MR0) controls the PWM cycle rate, by resetting the count upon match. The other match register controls the PWM edge position. Additional  single edge controlled PWM outputs require only one match register each, since the repetition rate is the same for all PWM outputs. Multiple single edge controlled PWM outputs will all have a rising edge at the beginning of each PWM cycle, when an MR0 match occurs. Three match registers can be used to  provide a PWM output with both edges controlled. Again, the MR0 match register controls the PWM cycle rate. The other match registers control the two PWM edge positions. Additional double edge controlled PWM outputs require only two match registers each, since the repetition rate is the same for all PWM outputs. With double edge controlled PWM outputs, specific match registers control the rising and falling edge of the output. This allows both positive going PWM pulses (when the rising edge occurs prior to the falling edge), and negative going PWM pulses (when the falling edge occurs prior to the rising edge).
3.6.18.1 Features
1)      Seven match registers allow up to six single edge controlled or three double edge controlled PWM outputs, or a mix of both types.
2)      The match registers also allow:
a)      Continuous operation with optional interrupt generation on match.
b)      Stop timer on match with optional interrupt generation.
c)      Reset timer on match with optional interrupt generation.
3)      Supports single edge controlled and/or double edge controlled PWM outputs. Single edge controlled PWM outputs all go HIGH at the beginning of each cycle unless the output is a constant LOW. Double edge controlled PWM outputs can have either edge occur at any position within a cycle. This allows for both positive going and negative going pulses.
4)      Pulse period and width can be any number of timer counts. This allows complete flexibility in the trade-off between resolution and repetition rate. All PWM outputs will occur at the same repetition rate.
5)      Double edge controlled PWM outputs can be programmed to be either positive going or negative going pulses.
6)      Match register updates are synchronized with pulse outputs to prevent generation of erroneous pulses. Software must ‘release’ new match values before they can become effective.
7)      May be used as a standard timer if the PWM mode is not enabled.
8)      A 32-bit Timer/Counter with a programmable 32-bit Prescaler.
3.6.19 System control
3.6.19.1 Crystal oscillator
On-chip integrated oscillator operates with external crystal in range of 1 MHz to 25 MHz. The oscillator output frequency is called fosc and the ARM processor clock frequency is referred to as CCLK for  urposes of rate equations, etc. fosc and CCLK are the same  value unless the PLL is running and
3.6.19.2 PLL
The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input frequency is multiplied up into the range of 10 MHz to 60 MHz with a Current Controlled Oscillator (CCO). The multiplier can be an integer value from 1 to 32 (in practice, the multiplier value cannot be higher than 6 on this family of microcontrollers due to the upper frequency limit of the CPU). The CCO operates in the range of 156 MHz to 320 MHz, so there is an additional divider in the loop to keep the CCO within its frequency range while the PLL is providing the desired output frequency. The output divider may be set to divide by 2, 4, 8, or 16 to produce the output clock. Since the minimum output divider value is 2, it is insured that the PLL output has a 50 % duty cycle. The PLL is turned off and bypassed following a chip reset and may be enabled by software. The program must configure and activate the PLL, wait for the PLL to Lock, then connect to the PLL as a clock source. The PLL settling time is 100 s.
3.6.19.3 Reset and wake-up timer
Reset has two sources on the LPC2141/42/44/46/48: the RESET pin and watchdog reset. The RESET pin is a Schmitt trigger input pin with an additional glitch filter. Assertion of chip reset by any source starts the Wake-up Timer (see Wake-up Timer description below), causing the internal chip reset to remain asserted until the external reset is de-asserted, the oscillator is running, a fixed number of clocks have passed, and the on-chip flash controller has completed its initialization. When the internal reset is removed, the processor begins executing at address 0, which is the reset vector. At that point, all of the processor and peripheral registers have been initialized to predetermined values. The Wake-up Timer ensures that the oscillator and other analog functions required for chip operation are fully functional before the processor is allowed to execute instructions. This is important at power on, all types of reset, and whenever any of the aforementioned functions are turned off for any reason. Since the oscillator and other functions are turned off during Power-down mode, any wake-up of the processor from Power-down mode makes use of the Wake-up Timer. The Wake-up Timer monitors the crystal oscillator as the means of checking whether it is safe to begin code execution. When power is applied to the chip, or some event caused the chip to exit Power-down mode, some time is required for the oscillator to produce a signal of sufficient amplitude to drive the clock logic. The amount of time depends on many factors, including the rate of VDD ramp (in the case of power on), the type of crystal and its electrical characteristics (if a quartz crystal is used), as well as any other external circuitry (e.g. capacitors), and the characteristics of the  oscillator itself under the existing ambient conditions.
3.6.19.4 Brownout detector
The LPC2141/42/44/46/48 include 2-stage monitoring of the voltage on the VDD pins. If this voltage falls below 2.9 V, the BOD asserts an interrupt signal to the VIC. This signal can be enabled for interrupt; if not, software can monitor the signal by reading dedicated register. The second stage of low voltage   detection asserts reset to inactivate the LPC2141/42/44/46/48 when the voltage on the VDD pins falls below 2.6 V. This reset prevents alteration of the flash as operation of the various elements of the chip would otherwise become unreliable due to low voltage. The BOD circuit maintains this reset down below 1 V, at which point the POR circuitry maintains the overall reset. Both the 2.9 V and 2.6 V thresholds include some hysteresis. In normal operation, this hysteresis allows the 2.9 V detection to reliably  interrupt, or a regularly-executed event loop to sense the condition.
3.6.19.5 Code security
This feature of the LPC2141/42/44/46/48 allow an application to control whether it can be debugged or protected from observation. If after reset on-chip boot loader detects a valid checksum in flash and  reads 0x8765 4321 from address 0x1FC in flash, debugging will be disabled and thus the code in flash will be protected from observation. Once debugging is disabled, it can be enabled only by performing a full chip erase using the ISP.
3.6.19.6 External interrupt inputs
The LPC2141/42/44/46/48 include up to nine edge or level sensitive External Interrupt Inputs as selectable pin functions. When the pins are combined, external events can be processed as four  independent interrupt signals. The External Interrupt Inputs can optionally be used to wake-up the  processor from Power-down mode. Additionally capture input pins can also be used as external interrupts without the option to wake the device up from Power-down mode.
3.6.19.7 Memory mapping control
The Memory Mapping Control alters the mapping of the interrupt vectors that appear beginning at  address 0x0000 0000. Vectors may be mapped to the bottom of the on-chip flash memory, or to the on-chip static RAM. This allows code running in different memory spaces to have control of the interrupts.
3.6.19.8 Power control
The LPC2141/42/44/46/48 supports two reduced power modes: Idle mode and Power-down mode.In Idle mode, execution of instructions is suspended until either a reset or interrupt occurs. Peripheral functions continue operation during Idle mode and may generate interrupts to cause the processor to resume execution. Idle mode eliminates power used by the processor itself, memory systems and related controllers, and internal buses. In Power-down mode, the oscillator is shut down and the chip receives no internal clocks. The processor state and registers, peripheral registers, and internal SRAM values are preserved throughout Power-down mode and the logic levels of chip output pins remain static. The Power-down mode can be terminated and normal operation resumed by either a reset or certain specific interrupts that are able to function without clocks. Since all dynamic operation of the chip is suspended, Power-down mode reduces chip power consumption to nearly zero. Selecting an external 32 kHz clock instead of the PCLK as a clock-source for the on-chip RTC will enable the microcontroller to have the RTC active during Power-down mode. Power-down current is increased with RTC active. However, it is significantly lower than in Idle mode. A Power Control for Peripherals feature allows individual peripherals to be turned off if they are not needed in the application, resulting in additional power savings during  active and Idle mode.
3.6.19.9 APB bus
The APB divider determines the relationship between the processor clock (CCLK) and the clock used by peripheral devices (PCLK). The APB divider serves two purposes. The first is to provide peripherals with the desired PCLK via APB bus so that they can operate at the speed chosen for the ARM processor. In order to achieve this, the APB bus may be slowed down to 12 to 14 of the processor clock rate. Because the APB bus must work properly at power-up (and its timing cannot be altered if it does not work since the APB divider control registers reside on the APB bus), the default condition at reset is for the APB bus to run at 14 of the processor clock rate. The second purpose of the APB divider is to allow power savings when an application does not require any peripherals to run at the full processor rate. Because the APB divider is connected to the PLL output, the PLL remains active (if it was running) during Idle mode.
3.6.20 Emulation and debugging
The LPC2141/42/44/46/48 support emulation and debugging via a JTAG serial port. A trace port  allows tracing program execution. Debugging and trace functions are multiplexed only with GPIOs on Port 1. This means that all communication, timer and interface peripherals residing on Port 0 are available  during the development and debugging phase as they are when the application is run in the embedded system itself.
3.6.20.1 EmbeddedICE
Standard ARM EmbeddedICE logic provides on-chip debug support. The debugging of the target system requires a host computer running the debugger software and an EmbeddedICE protocol  convertor. EmbeddedICE protocol convertor converts the remote debug protocol commands to the JTAG data needed to access the ARM core. The ARM core has a Debug Communication Channel (DCC)  function built-in. The DCC allows a program running on the target to communicate with the host debugger or another separate host without stopping the program flow or even entering the debug state. The DCC is accessed as a co-processor 14 by the program running on the ARM7TDMI-S core. The DCC allows the JTAG port to be used for sending and receiving data without affecting the normal program flow. The DCC data and control registers are mapped in to  addresses in the EmbeddedICE logic. This clock must be  slower than 16 of the CPU clock (CCLK) for the JTAG interface to operate.
3.6.20.2 Embedded trace
Since the LPC2141/42/44/46/48 have significant amounts of on-chip memory, it is not possible to determine how the processor core is operating simply by observing the external pins. The Embedded Trace Macrocell (ETM) provides real-time trace capability for deeply embedded processor cores. It outputs information about processor execution to the trace port. The ETM is connected directly to the ARM core and not to the main AMBA system bus. It compresses the trace information and exports it through a narrow trace port. An external trace port analyzer must capture the trace information under software debugger control.  Instruction trace (or PC trace) shows the flow of execution of the processor and provides a  list of all the instructions that were executed. Instruction trace is significantly compressed by only broadcasting branch addresses as well as a set of status signals that indicate the pipeline status on a cycle by cycle basis. Trace information generation can be controlled by selecting the trigger  resource. Trigger resources include address comparators, counters and sequencers. Since trace  information is compressed the software debugger requires a static image of the code being executed. Self-modifying code can not be traced because of this restriction.
3.6.20.3 RealMonitor
RealMonitor is a configurable software module, developed by ARM Inc., which enables real-time debug. It is a lightweight debug monitor that runs in the background while users debug their foreground application. It communicates with the host using the DCC, which is present in the EmbeddedICE logic. The LPC2141/42/44/46/48 contain a specific configuration of RealMonitor software programmed into the on-chip flash memory.









CHAPTER 4
hardware development
4.1 Design overview:
The Block diagram given below consists of a Fingerprint scanner, a GPS modem, a GSM modem, a LPC2148 Microcontroller, an IR transmitter, an IR receiver, an enrolling switch, an on/off switch, a LCD Display and power supply.  These hardware components will be discussed briefly as follows:
Fingerprint processing consists of two process: fingerprint logon process and the fingerprint matching process which is divided into fingerprint matching  fingerprint matching (1:1) and fingerprint search (1:n) in two ways. Fingerprint login, fingerprint entry for each one 2times 2 times the input of image processing, synthetic templates stored in the module. Fingerprint match, the first through the fingerprint sensor to verify the fingerprint image input and processing, and then with the module to match the fingerprint template comparison.
A GPS modem is used to get the signals and receive the signals from the satellites.   In this project, GPS modem get the signals from the satellites and those are given to the microcontroller.  The signals may be in the form of the coordinates; these are represented in form of the latitudes, longitudes and altitudes. 
A GSM modem is used to get the messages from the mobile and as well as reading the message also.  Thereafter sending the acknowledgement will be done.  Before operating this GSM modem first we have to insert the SIM card in this modem.  Then the total receiving and sending the messages will be done based on this number.  First the concerned person has to register for that number.
A Micro controller is a heart of this project.  The total controlling action will be done through this micro controller. Based on the signals given to the micro controller that will be totally controlled at the output section.  If we send the message like “STOP” to the GSM modem, it will send signals to the micro controller to stop the vehicle.  Upon receiving the signals, the micro controller will switched-off the ignition part of that vehicle. Then the vehicle does not start until we send START message.

An ignition switch plays the key role in the vehicle, for moving.  If it is in off condition, the vehicle does not move at an inch.  In this project, for completely stopping the vehicle we are just switched-off the ignition switch with the help of the micro controller. A LCD display is used at the output section.  To display the status of the GSM and GPS.  The maximum power supply required to operate the hardware circuitry is +5V DC voltage. An IR transmitter and an IR receiver is used to activate the fingerprint module and to give user ID. An enrolling switch is used to allow authorization to the other persons while the authorized person is logged in through fingerprint module.
4.2 Block diagram:


4.3 Hardware components required:
For the implementation of fingerprint protected anti theft tracking system we required some important components. Those are:
1.                  Fingerprint module
2.                  LPC2148 Microcontroller(consists ARM7TDMI-S processor)
3.                  GPS module
4.                  GSM module
5.                  Switches
6.                  Vibration sensor
7.                  Motor and its driving circuit
8.                  230/18V step down transformer
9.                  Bridge rectifier
4.4 Fingerprint module:
A fingerprint sensor is an electronic device used to capture a digital image of the fingerprint pattern. The captured image is called a live scan. This live scan is digitally processed to create a biometric template (a collection of extracted features) which is stored and used for matching.
4.4.1 General Descriptions:
FIM30 is an evolutionary standalone fingerprint recognition module consisted of optic sensor and processing board. As CPU and highly upgraded algorithm are embedded into a module, it provides high recognition ratio even to small size, wet, dry, calloused fingerprint. High speed 1: N identification and 1: N verification.
Fingerprint processing consisting of two process: fingerprint logon process and the fingerprint matching process [which is divided into fingerprint matching fingerprint matcing [1:1] and fingerprint search (1:N) in two ways].
Fingerprint login, fingerprint entry for each one 2times e times the input of image processing, synthetic templates stored I the module. Fingerprint match, the first through the fingerprint sensor to verify the fingerprint image input and processing, and then with the module to match the fingerprint template comparison (If specified in the module to match a template, called the fingerprint matching method, namely, 1:N mode), the module gives the matching results (pass or fail.)
4.4.2 Key Function:
FIM30N supports 3 function key inputs such as Enroll Key, Delete Key, and Identify Key. Using these keys without serial communication, enrollment, deletion, all deletion and identification operating can be executed. The following timing diagram and table show the operation condition of keys. FIM 30 has functions of fingerprint enrollment, identification, partial and entire deletion and reset in a single board, it does not require connection with a separate PC, thereby offering convenient development environment.  Off-line functionality stores logs on the equipment memory (up to 100 fingerprints) and it’s identified using search engine from the internal algorithm.  Evolutionary standalone fingerprint recognition module FIM30 is ideal for on-line applications, because allows ASCII commands to manage the device from the host.  On-line functionality, fingerprints to verify (1:1) or identify (1: N) can be stored on non volatile memory, or be sent by RS-232 port.  This FIM 3030 is going to have the Optical Sensor to Enroll and Identify the Finger Print.
4.4.3 Optical sensor:
Optical fingerprint imaging involves capturing a digital image of the print using visible light. This type of sensor is, in essence, a specialized digital camera. The top layer of the sensor, where the finger is placed, is known as the touch surface. Beneath this layer is a light-emitting phosphor layer which illuminates the surface of the finger. The light reflected from the finger passes through the phosphor layer to an array of solid state pixels (a charge-coupled device) which captures a visual image of the fingerprint. A scratched or dirty touch surface can cause a bad image of the fingerprint. A disadvantage of this type of sensor is the fact that the imaging capabilities are affected by the quality of skin on the finger. For instance, a dirty or marked finger is difficult to image properly. Also, it is possible for an individual to erode the outer layer of skin on the fingertips to the point where the fingerprint is no longer visible. It can also be easily fooled by an image of a fingerprint if not coupled with a "live finger" detector. However, unlike capacitive sensors, this sensor technology is not susceptible to electrostatic discharge damage.
4.4.4 Why go for Biometrics?

A list of some of the strengths, weaknesses and suitable applications for each biometric methodology a list of some of the strengths, weaknesses and suitable applications for each biometric methodology.



 1)      Authentication – the process of verifying that a user requesting a network resource is who he, she, or it claims to be, and vice versa.
2)      Conventional authentication methods
a)      something that you have – key, magnetic card or smartcard
b)      something that you know – PIN or password
3)      Biometric authentication uses personal features
a)      something that you are
4.4.5 Advantages:
     Biometrics has no risk of
1)      Forgetting it
2)      Loosing it
3)      Getting it stolen
4)      Getting it copied
5)      Being used by anyone else.
4.4.6 Essential Properties of a Biometric:
1)      Universal
a)      Everyone should have the characteristic
2)      Uniqueness
a)      No two persons have the same characteristic
3)      Permanence
a)      Characteristic should be unchangeable
4)      Collectability
a)      Characteristic must be measurable
4.4.7 Biometric System Process Flow:
 4.4.8 Pattern Recognition:
1)      Description and classification of measurements taken from physical or mental processes
2)      Examination of pattern characteristics
3)      Formulation of the recognition system
4)      Important part of any biometric system
4.4.9 Why Fingerprint biometry?
1)      High Universality
a)      A majority of the population (>96%) have legible fingerprints
b)      More than the number of people who possess passports, license and IDs
2)      High Distinctiveness
a)      Even identical twins have different fingerprints (most biometrics fail)
b)      Individuality of fingerprints established through empirical evidence
3)      High Permanence
a)      Fingerprints are formed in the fetal stage and remain structurally unchanged through out life.
b)      One of the most accurate forms of biometrics available
c)      Best trade off between convenience and security
4)      High Acceptability
a)      Fingerprint acquisition is non intrusive. Requires no training.

4.4.10  Advantages:
1)      Uniqueness
2)      Surety over the Cards and Keypads
3)      Against to Cards Duplication, misplacement and improper disclosure of password
4)      No excuses for RF/Magnetic Cards forget ness
5)      No need to further invest on the Cards Cost
6)      No need to further manage the Cards Writing Devices
4.4.11 Fingerprint Patterns
1)      Loops
a)      Ridge lines enter from one side and curve around to exit from the same side
b)      60-65% of population
2)      Whorls
a)      Rounded or circular ridge pattern
b)      30-35% of population
3)      Arches
a)      Ridge lines enter from one side of print and exit out the other
b)      5% of population
 Major technical indicators
1)      Supply voltage: 5V
2)      Supply current:
3)      Current: 100mA
4)      Peak current: 150mA
5)      Fingerprint image input time: <0.5 second window area 14”18mm
6)      Matching:
7)      Comparison method(1:1)
8)      Search mode(1:N) profile:256 bytes
9)      Template file: 512 bytes
10)  Storage capacity: 900
11)  Security level: five(from low to high: 1,2,3,4,5)
12)  False Accept Rate (FAR):<0.001%(safety class3)
13)  False rejection rate(FRR): <0.1% (safety class3)
14)  Search time:<1.0 seconds (1:1000, the mean value)
15)  PC interface: UART (TTL logic level) or USB1.1
16)  Communications baud rate (UART): (9600*N)bps where N=1~12(default N=6, ie 57600bps)
17)  Storage environment:
18)  Temperature: -40 C - +85C
 1                    1 VCC in 5V power input (input supply voltage range can be 3.6 ~ 7.5V)
2                    TXD out the serial port transmitter
3                    RXD in serial port receiver
4                    GND – system ground
5                    KEYPOWER – power IC’s power supply should be input, input voltage is 5V (input supply voltage range can be 3.6 ~ 7.5V)
6                    OUT – output of the power sensor, usually high output of 3.3V, when a finger touches the sensing area, this pin outputs low.
4.4.12 Serial protocol:
     Halfn – duplex asynchronous serial communication recognize wave. Olmert was 57600bos, set by command 9600 ~ 115200bps
Frame format is 10 bits, a 0-level start bit, 8 data bits (LSB first)  and a stop bit, no parity

POWER-ON DELAY TIME
      Power module, the initialization time is about 500mS. During this period, the module can not respond to the host computer command.
4.4.13 Fingerprint Database:
Opened in the FLASH module I a fingerprint template storage area as a storage area, commonly known as the  fingerprint database. Fingerprint library data is power protection. Fingerprint template stored in accordance with the serial nuber, if the fingerprint storage capacity of N, the fingerprint template in the fingerprint library number is defined as:0,1,2,…..N-2,N-1. Users can only access the fingerprint database based on the content of serial number.

4.5 IR-SENSOR

Infrared (IR) radiation is part of the electromagnetic spectrum, which includes radio waves, microwaves, visible light, and ultraviolet light, as well as gamma rays and X-rays. The IR range falls between the visible portion of the spectrum and radio waves. IR wavelengths are usually expressed in microns, with the lR spectrum extending from  0.7 to 1000microns. Using advanced optic systems and detectors, non-contact IR thermometers can focus on nearly any portion or portions of the 0.7-14 micron band. Because every object (with the exception of a blackbody) emits an optimum amount of IR energy at a specific point along the IR band, each process may require unique sensor models with specific optics and detector types. For example, a sensor with a narrow spectral range center data 3.43 microns is optimized for measuring the surface temperature of polyethylene and related materials. A sensor set up for 5 microns is used to measure glass surfaces. A micron sensor is used for metals and foils. The broader spectral ranges are used to measure lower temperature surfaces, such as paper, board, poly, and foil composites.
The intensity of an object's emitted IR energy increases or decreases in proportion to its temperature. It is the emitted energy, measured as the target's emissivity that indicates an object's temperature. Emissivity is a term used to quantify the energy-emitting characteristics of different materials and surfaces. IR sensors have adjustable emissivity settings, usually from 0.1 to 1.0, which allow accurate temperature measurements of several surface types. The emitted energy comes from an object and reaches the IR sensor through its optical system, which focuses the energy onto one or more photosensitive detectors. The detector then converts the IR energy into an electrical signal, which is in turn converted into a temperature value. Based on the sensor's calibration equation and the target's emissivity. This temperature value can be displayed on the sensor or, in the case of the smart sensor, converted to a digital output and displayed on a computer terminal. IR remote controls use wavelengths between 850 - 950nm. At this short wavelength, the light is invisible to the human eye, but a domestic camcorder can actually view this portion of the electromagnetic spectrum. Viewed with a camcorder, an IR LED appears to change brightness.
All remote controls use an encoded series of pulses, of which there are thousands of combinations. The light output intensity varies with each remote control, remotes working at 4.5V dc generally will provide a stronger light output than a 3V dc control. Also, as the photodiode in this project has a peak light response at 850nm, it will receive a stronger signal from controls operating closer to this wavelength. The photodiode will actually respond to IR wavelengths from 400nm to 1100nm,so all remote controls should be compatible.
A sensor is a type of transducer, or mechanism, that responds to a type of energy by producing another type of energy signal, usually electrical. They are either direct indicating (an electrical meter) or are paired with an indicator (perhaps indirectly through an analog to digital converter, a computer and a display) so that the value sensed is translated for human understanding. Types of sensors include electromagnetic, chemical, biological and acoustic. Aside from other applications, sensors are heavily used in medicine, industry& robotics.
In order to act as an effectual sensor, the following guidelines must be met:
  • the sensor should be sensitive to the measured property
  • the sensor should be insensitive to any other property
  • the sensor should not influence the measured property
In theory, when the sensor is working perfectly, the output signal of a sensor is exactly proportional to the value of the property it is meant to measure. The gain is then defined as the ratio between output signal and measured property. For example, if a sensor measures temperature and has an actual voltage output, the gain is a constant with the unit.

     When the sensor is not perfect, various deviations can occur, including gain error, long term drift, and noise. These and other deviations can be classified as systematic, or random, errors. Systematic deviations may be compensated for by means of some kind of calibration strategy. Noise is an example of a random error that can be reduced by signal processing, such as filtering, usually at the expense of the dynamic behavior of the sensor.
A sensor network is a computer network of spatially distributed devices using sensors to monitor conditions (such as temperature, sound, vibration, pressure, motion or pollutants) at a variety of locations. Usually the devices are small and inexpensive, allowing them to be produced and deployed in large numbers; this constrains their resources in terms of energy, memory, and computational speed and bandwidth. Each device is equipped with a radio transceiver, a small micro controller, and an energy source, most commonly a battery. The devices work off each other to deliver data to the computer which has been set up to monitor the information. Sensor networks involve three areas: sensing, communications, and computation (hardware, software, algorithms). They are applied in many areas, such as video surveillance, traffic monitoring, home monitoring and manufacturing. Here the IR transmitter is nothing but the IR LED. It just looks like a normal LED but transmits the IR signals. Since the IR rays are out of the visible range we cannot observe the rays from the transmitter. These are infrared LEDs; the light output is not visible by our eyes. They can be used as replacement LEDs for remote controls, night vision for camcorders, invisible beam sensors, etc.
Infrared LEDs are ideal light sources for use with night vision goggles, surveillance cameras, medical imaging, recognition and calibration systems.
 4.5.1 Advantages:
           Due to their resistance to ambient-light impediments and electromagnetic interference (EMI), Infrared LEDs enhance the performance of wireless computer-to-PDA links, collision avoidance systems, automation equipment, biomedical instrumentation, and telecommunications equipment.
           Solid-state design renders Infrared LEDs impervious to electrical and mechanical shock, vibration, frequent switching and environmental extremes. With an average life span of 100,000-plus hours (11 years), Infrared LEDs operate reliably year-after-year.
4.5.2 IR RECEIVER (TSOP):
The TSOP17– Series are miniaturized receivers for infrared remote control systems. PIN diode and preamplifier are assembled on lead frame, the epoxy package is designed as IR filter. The demodulated output signal can directly be decoded by a microprocessor. TSOP17.. is the standard IR remote control receiver series, supporting all major transmission codes.
Features
·                     Photo detector and preamplifier in one package
·                     Internal filter for PCM frequency
·                     Improved shielding against electrical field disturbance
·                     TTL and CMOS compatibility
·                     Output active low
·                     Low power consumption
·                     High immunity against ambient light
·                     Continuous data transmission possible (up to 2400 bps)
·                     Suitable burst length .10 cycles/burst

 4.5.3 Suitable Data Format
The circuit of the TSOP17 is designed in that way that unexpected output pulses due to noise or disturbance signals are avoided. A bandpass filter, an integrator stage and an automatic gain control are used to suppress such disturbances. The distinguishing mark between data signal and disturbance signal are carrier frequency, burst length and duty cycle. The data signal should fulfill the following condition• Carrier frequency should be close to center frequency of the band pass (e.g. 38 kHz). Burst length should be 10 cycles/burst or longer. • After each burst which is between 10 cycles and 70cycles a gap time of at least 14 cycles is necessary.  For each burst, which is longer than 1.8ms, a corresponding gap time is necessary at some time in the data stream. This gap time should have at least same length as the burst. • Up to 1400 short bursts per second can be received continuously. Some examples for suitable data format are: NEC Code, Toshiba Micom Format, Sharp Code, RC5 Code, RC6 Code, R–2000 Code, Sony Format (SIRCS).When a disturbance signal is applied to the TSOP17. it can still receive the data signal. However the sensitivity is reduced to that level that no unexpected pulses will occur. Some examples for such disturbance signals which are suppressed by the TSOP17are:
• DC light (e.g. from tungsten bulb or sunlight)
• Continuous signal at 38kHz or at any other frequency  Signals from fluorescent lamps with electronic ballast.
4.6 GLOBAL POSITION SYSTEM
4.6.1 About GPS
Global Positioning System (GPS) technology is changing the way we work and play. You can use GPS technology when you are driving, flying, fishing, sailing, hiking, running, biking, working, or exploring. With a GPS receiver, you have an amazing amount of information at your fingertips. Here are just a few examples of how you can use GPS technology.
  • Know precisely how far you have run and at what pace while tracking your path so you can find your way home.
  • Pinpoint the perfect fishing spot on the water and easily relocate it.
  • Get the closest location of your favorite restaurant when you are out-of-town.
  • Find the nearest airport or identify the type of airspace in which you are flying
4.6.2 What is GPS?
The Global Positioning System (GPS) is a satellite-based navigation system that sends and receives radio signals. A GPS receiver acquires these signals and provides you with information. Using GPS technology, you can determine location, velocity, and time, 24 hours a day, in any weather conditions anywhere in the world—for free.
GPS, formally known as the NAVSTAR (Navigation Satellite Timing and Ranging). Global Positioning System originally was developed for the military. Because of its popular navigation capabilities and because you can access GPS technology using small, inexpensive equipment, the government made the system available for civilian use. The USA owns GPS technology and the Department of Defense maintains it.
GPS technology requires the following three segments.
·                     Space segment.
·                     Control segment.
·                     User segment
Space Segment
At least 24 GPS satellites orbit the earth twice a day in a specific pattern. They travel at approximately 7,000 miles per hour about 12,000 miles above the earth’s surface. These satellites are spaced so that a GPS receiver anywhere in the world can receive signals from at least four of them.
·                     Each GPS satellite constantly sends coded radio signals (pseudorandom code) to the earth. These GPS satellite signals contain the following information.
·                     The particular satellite that is sending the information.
·                     Where that satellite should be at any given time (the precise location of the satellite is. called ephemeris data).
·                     Whether or not the satellite is working properly.
·                     The date and time that the satellite sent the signal.
The signals can pass through clouds, glass, and plastic. Most solid objects such as buildings attenuate (decrease the power of) the signals. The signals cannot pass through objects that contain a lot of metal or objects that contain water (such as underwater locations). The GPS satellites are powered by solar energy. If solar energy is unavailable, for example, when the satellite is in the earth’s shadow, satellites use backup batteries to continue running. Each GPS satellite is built to last about 10 years. The Department of Defense monitors and the satellites to ensure that GPS technology continues to run smoothly for years to come.
 Control Segment
The control segment is responsible for constantly monitoring satellite health, signal integrity, and orbital configuration from the ground control segment includes the following sections:
·                     Master control station
·                     Monitor stations
·                     Ground antennas
Monitor Stations
At least six unmanned monitor stations are located around the world. Each station constantly monitors and receives information from the GPS satellites and then sends the orbital and clock information to the master control station (MCS).
Master Control Station (MCS)
The MCS) is located near Colorado Springs in Colorado. The MCS constantly receives GPS satellite orbital and clock information from monitor stations. The controllers in the MCS make precise corrections to the data as necessary, and send the information (known as ephemeris data) to the GPS satellites using the ground antennas.
Ground Antennas
Ground antennas receive the corrected orbital and clock information from the MCS, and then send the corrected information to the appropriate satellites.
User Segment
The GPS user segment consists of your GPS receiver. Your receiver collects and processes signals from the GPS satellites that are in view and then uses that information to determine and display your location, speed, time, and so forth. Your GPS receiver does not transmit any information back to the satellites.
4.6.3 How Does GPS Technology Work?
     The following points provide a summary of the technology at work:
1)      The control segment constantly monitors the GPS constellation and uploads information to satellites to provide maximum user accuracy
2)      Your GPS receiver collects information from the GPS satellites that are in view.
3)      Your GPS receiver accounts for errors. For more information, refer to the Sources of Errors.
4)      Your GPS receiver determines your current location, velocity, and time.
5)      Your GPS receiver can calculate other information, such as bearing, track, trip distance, and distance to destination, sunrise and sunset time so forth.
6)      Your GPS receiver displays the applicable information on the screen.
4.6.4 Who Uses GPS?
GPS technology has many amazing applications on land, at sea, and in the air. You might be surprised to learn about the following examples of how people or professions are already using GPS technology
Agriculture:
In precision farming, GPS technology helps monitor the application of fertilizer and pesticides. GPS technology also provides location information that helps farmers plow, harvest, map fields, and mark areas of disease or weed infestation.
Aviation:
Aircraft pilots use GPS technology for en route navigation and airport approaches. Satellite navigation provides accurate aircraft location anywhere on or near the earth.
Environment:
GPS technology helps survey disaster areas and maps the movement of environmental phenomena (such as forest fires, oil spills, or hurricanes). It is even possible to find locations that have been submerged or altered by natural disasters.
Ground Transportation:
GPS technology helps with automatic vehicle location and in-vehicle navigation systems. Many navigation systems show the vehicle’s location on an electronic street map, allowing drivers to keep track of where they are and to look up other destinations. Some systems automatically create a route and give turn-by-turn directions. GPS technology also helps monitor and plan routes for delivery vans and emergency vehicles.
Marine:
GPS technology helps with marine navigation, traffic routing, underwater surveying, navigational hazard location, and mapping. Commercial fishing fleets use it to navigate to optimum fishing locations and to track fish migrations.
Military:
Military aircraft, ships, submarines, tanks, jeeps, and equipment use GPS technology for many purposes including basic navigation, target designation, close air support, weapon technology, and rendezvous.
Public Safety:
Emergency and other specialty fleets use satellite navigation for location and status information.
Rail:
Precise knowledge of train location is essential to prevent collisions, maintain smooth traffic flow, and minimize costly delays. Digital maps and onboard inertial units allow fully-automated train control.
Recreation:
Outdoor and exercise enthusiasts use GPS technology to stay apprised of location, heading, bearing, speed, distance, and time. In addition, they can accurately mark and record any location and return to that precise spot.
Space:
GPS technology helps track and control satellites in orbit. Future booster rockets and reusable launch vehicles will launch, orbit the earth. Return, and land, all under automatic control. Space shuttles also use GPS navigation.
Surveying:
Surveyors use GPS technology for simple tasks (such as defining property lines) or for complex tasks (such as building infrastructures in urban centers). Locating a precise point of reference used to be very time consuming. With GPS technology, two people can survey dozens of control points in an hour. Surveying and mapping roads and rail systems can also be accomplished from mobile platforms to save time and money.
Timing:
Delivering precise time to any user is one of the most important functions of GPS technology. This technology helps synchronize clocks events around the world. Pager companies depend on GPS satellites to synchronize the transmission of information throughout their systems. Investment banking firms rely on this service every day to record international transactions simultaneously.
4.6.5 How Accurate Is GPS?
GPS technology depends on the accuracy of signals that travel from GPS satellites to a GPS receiver. You can increase accuracy by ensuring that when you use (or at least when you turn on) your GPS receiver, you are in an area with few or no obstacles between you and the wide open sky. When you first turn on your GPS receiver, stand in an open area for a few moments to allow the unit to get a good fix on the satellites (especially if you are heading into an obstructed area). This gives you better accuracy for a longer period of time (about 4-6 hours). It takes between 65 and 85 milliseconds for a signal to travel from GPS satellite to a GPS receiver on the surface of the earth.
 The signals are so accurate that time can be figured to much less than a millionth of a second, velocity can be figured to within a fraction of a mile per hour, and location can be figured to within a few meters.
WAAS/EGNOS:
The Wide Area Augmentation System (WAAS) is a system of satellites and ground stations that provides even better position accuracy than the already highly accurate GPS. Europe’s version of this system is the European Geostationary Navigation Overlay Service (EGNOS). The Federal Aviation Administration (FAA) developed the WAAS program. It makes more airspace usable to pilots, provides more direct end route paths, and provides new precision approach services to runways, resulting in safety and capacity improvements in all weather conditions at all locations throughout the U.S. National Airspace System (NAS).
Although it was designed for aviation users, WAAS supports a wide variety of other uses, for example, more precise marine navigation. To take advantage of WAAS technology, you must have a WAAS-capable GPS receiver in an area where WAAS satellite coverage is available such as North America. No additional equipment or fees are required to take advantage of WAAS.
Sources of Errors:
Errors can affect the accuracy of the GPS signal. Take your GPS receiver to an area with a wide and unobstructed view of the sky to reduce the possibility and impact of some errors. Here are some of the most common GPS errors.
Ionosphere and Troposphere Delays:
The satellite signal slows down as it passes through the atmosphere. The system uses a built-in model that calculates an average delay to partially correct this type of error.
Orbital Errors:
This terminology refers to inaccuracies of the satellite’s reported location.
Receiver Clock Errors:
The GPS receiver has a built-in clock that can have small timing errors.
Number of Satellites Visible:
Obstructions can block signal reception, causing position errors or no position reading. The more satellites that your GPS receiver can view, the better the fix is.
Satellite Geometry/Shading:
Refers to the relative position of the satellites at any given time. Ideal satellite geometry exists when the satellites are located at wide angles relative to each other. Poor geometry results when the satellites are located in a line or in a tight grouping.
Signal Multipath:
The GPS signal bounces off of objects, such as tall buildings or large rock surfaces, before it reaches the GPS receiver. This increases the travel time of the signal and, therefore, causes errors.
Buying a GPS Receiver:
Deciding which GPS receiver to buy can be overwhelming. Think about how you want to use the unit, for example, traveling or running. Keep the following considerations in mind:
Product Level
     Do you want the basics, or do you want all of the bells and whistles? You can find a unit that fits your needs and budget.
Power Source:
Will you be using the unit away from an auxiliary power source? You might need to carry extra batteries. With some you can use a vehicle adapter or AC power source.
Portability:
Do you have a preference between a portable or a built-in unit? Some units mount directly in the dashboard of your boat or aircraft.
Mapping Capability:
Do you want to know the general direction or street-level details of your chosen path? Map data can include streets restaurants, tourist attractions, marine data, topography, and so forth.
Mounts:
A mount for your GPS can be useful to keep your hands free while navigating your bike, boat, car, or airplane. Many units with a mount, and several additional mounts are available.
Ease of Use:
Some receivers provide a tutorial or an easy-to-use touch screen interface. Some even have turn-by-turn voice instructions you are navigating your route.
Antenna Configuration:
Where are you going to use the unit? With some units, you use only the built-in antenna. With other units, you attach an external antenna to give you better reception

Price:
Which units fit your price range? An inexpensive entry-level unit can be a great way to enter the GPS world.
Software:
Whether you want to save your favorite locations or plan a trip, map software can help. You can use your PC or go directly your GPS receiver. Your preference for map detail and your specific activities determine which software is right for you.
Complementary Navigation Aids:
Remember, a GPS receiver is a complement to navigation and should not be the only navigational tool that you use. Using a paper map, a simple compass, and having knowledge of manual navigation is a good, safe practice.
4.6.6 Pin assignment:

 4.7 GLOBAL SYSTEM FOR MOBILE COMMUNICATION
4.7.1Definition:
Global system for mobile communication (GSM) is a globally accepted standard for digital cellular communication. GSM is the name of a standardization group established in 1982 to create a common European mobile telephone standard that would formulate specifications for a pan-European mobile cellular radio system operating at 900 MHz. It is estimated that many countries outside of Europe will join the GSM partnership.
4.7.2 Description:
GSM, the Global System for Mobile communications, is a digital cellular communications system, which has rapidly gained acceptance and market share worldwide, although it was initially developed in a European context. In addition to digital transmission, GSM incorporates many advanced services and features, including ISDN compatibility and worldwide roaming in other GSM networks. The advanced services and architecture of GSM have made it a model for future third-generation cellular systems, such as UMTS. This paper will give an overview of the services offered by GSM, the system architecture, the radio transmission 
 GSM Modem:
A GSM modem can be an external modem device, such as the Wavecom FASTRACK Modem.  Insert a GSM SIM card into this modem, and connect the modem to an available serial port on your computer.
A GSM modem can be a PC Card installed in a notebook computer, such as the Nokia Card Phone.
A GSM modem could also be a standard GSM mobile phone with the appropriate cable and software driver to connect to a serial port on your computer.  Phones such as the Nokia 7110 with a DLR-3 cable, or various Ericsson phones, are often used for this purpose.
A dedicated GSM modem (external or PC Card) is usually preferable to a GSM mobile phone.  This is because of some compatibility issues that can exist with mobile phones.  For example, if you wish to be able to receive inbound MMS messages with your gateway, and you are using a mobile phone as your modem, you must utilize a mobile phone that does not support WAP push or MMS.  This is because the mobile phone automatically processes these messages, without forwarding them via the modem interface.  Similarly some mobile phones will not allow you to correctly receive SMS text messages longer than 160 bytes (known as “concatenated SMS” or “long SMS”).  This is because these long messages are actually sent as separate SMS messages, and the phone attempts to reassemble the message before forwarding via the modem interface.  (We’ve observed this latter problem utilizing the Ericsson R380, while it does not appear to be a problem with many other Ericsson models.)
When you install your GSM modem, or connect your GSM mobile phone to the computer, be sure to install the appropriate Windows modem driver from the device manufacturer.  To simplify configuration, the Now SMS/MMS Gateway will communicate with the device via this driver.  An additional benefit of utilizing this driver is that you can use Windows diagnostics to ensure that the modem is communicating properly with the computer.
The Now SMS/MMS gateway can simultaneously support multiple modems, provided that your computer hardware has the available communications port resources.
4.7.3  SMART MODEM (GSM/GPRS)
Analogic’s GSM Smart Modem is a multi-functional, ready to use, rugged and versatile modem that can be embedded or plugged into any application. The Smart Modem can be customized to various applications by using the standard AT commands. The modem is fully type-approved and can directly be integrated into your projects with any or all the features of Voice, Data, Fax, SMS, and Internet etc.
Smart Modem kit contain the following items:
1)      Analogic’s GSM/GPRS Smart Modem
2)      SMPS based  power supply adapter.  
3)      dBi antenna with cable (optional: other types)
4)      Data cable (RS232)
5)      User Manual

PRODUCT DESCRIPTION:
The connectors integrated to the body, guarantee the reliable output and input connections. An extractible holder is used to insert the SIM card (Micro-SIM type). Status LED indicates the operating mode.
 Physical Characteristics
 
 Temperature Range:
Operating temperature: from -200C to +550C
Storage temperature:  from -250C to +700C
Installing the modem:
To install the modem, plug the device on to the supplied SMPS Adapter. For Automotive applications fix the modem permanently using the mounting slots (optional as per your requirement dimensions).       
Inserting/ Removing the SIM Card:
To insert or Remove the SIM Card, it is necessary to press the SIM holder ejector button with Sharp edged object like a pen or a needle. With this, the SIM holder comes out a little, then pulls it out and insert or remove the SIM Card
 Make sure that the ejector is pushed out completely before accessing the SIM Card holder do not remove the SIM card holder by force or tamper it (it may permanently damage). Place the SIM Card Properly as per the direction of the installation. It is very important that the SIM is placed in the right direction for its proper working condition
Connecting External Antenna: Connect GSM Smart Modem to the external antenna with cable end with SMA male. The Frequency of the antenna may be GSM 900/1800 MHz. The antenna may be ( 0 dbi, 3 dbi or short length L-type antenna) as per the field conditions and signal conditions.
DC Supply Connection 
The Modem will automatically turn ON when connection is given to it. The following is the Power Supply Requirement: 
 Connecting Modem to external devices:
RS232 can be used to connect to the external device through the D-SUB/ USB (for USB model only) device that is provided in the modem.
Connectors:
 Description of the interfaces:
The modem comprises several interfaces:
·                     LED Function including operating Status
·                     External antenna (via SMA)
·                     Serial and control link
·                     Power Supply (Via 2 pin Phoenix tm contact)
·                     SIM card holder
LED Status Indicator:
The LED will indicate different status of the modem:
OFF                             Modem Switched off
ON                              Modem is connecting to the network
Flashing Slowly          Modem is in idle mode
Flashing rapidly          Modem is in transmission/communication (GSM only) 
 Protecting Modem:
Do not expose to the modem to extreme conditions such as High temperatures, direct sunlight, High Humidity, Rain, Chemicals, Water, Dust etc. For these details see the specifications given.
·                     Do not drop, Shake or hit the Modem. (Warranty may void)
·                     The Modem should not be used in extreme vibrating conditions
·                     Handle the Antenna and cable with care.
4.7.4 AT commands features:
 Line settings:
A serial link handler is set with the following default values Autobaud, 8 bits data, 1 stop bit, no parity, flow control.
Ø  Command line
Ø  Commands always start with AT (which means attention) and finish with a <CR> character.
Ø  Information responses and result codes
Ø  Responses start and end with <CR><LF>,.
Ø  If command syntax is incorrect, an ERROR string is returned.
Ø  If command syntax is correct but with some incorrect parameters, the +CME ERROR: <Err> or +CMS ERROR: <SmsErr> strings are returned with different error codes.
Ø  If the command line has been performed successfully, an OK string is returned.
Ø  In some cases, such as “AT+CPIN?” or (unsolicited) incoming events, the product does not return the OK string as a response.
4.7.5 Services provided by GSM
GSM was designed having interoperability with ISDN in mind, and the services provided by GSM are a subset of the standard ISDN services. Speech is the most basic, and most important, teleservice provided by GSM.
In addition, various data services are supported, with user bit rates up to 9600 bps. Specially equipped GSM terminals can connect with PSTN, ISDN, Packet Switched and Circuit Switched Public Data Networks, through several possible methods, using synchronous or asynchronous transmission. Also supported are Group 3 facsimile service, videotex, and teletex. Other GSM services include a cell broadcast service, where messages such as traffic reports, are broadcast to users in particular cells.
A service unique to GSM, the Short Message Service, allows users to send and receive point-to-point alphanumeric messages up to a few tens of bytes. It is similar to paging services, but much more comprehensive, allowing bi-directional messages, store-and-forward delivery, and acknowledgement of successful delivery.
Supplementary services enhance the set of basic teleservices. In the Phase I specifications, supplementary services include variations of call forwarding and call barring, such as Call Forward on Busy or Barring of Outgoing International Calls. Many more supplementary services, including multiparty calls, advice of charge, call waiting, and calling line identification presentation will be offered in the Phase 2 specifications.

4.7.6 Architecture of the GSM network:

A GSM network is composed of several functional entities, whose functions and interfaces are specified. Figure 1 shows the layout of a generic GSM network. The GSM network can be divided into three broad parts. The Mobile Station is carried by the subscriber. The Base Station Subsystem controls the radio link with the Mobile Station. The Network Subsystem, the main part of which is the Mobile services Switching Center (MSC), performs the switching of calls between the mobile users, and between mobile and fixed network users. The MSC also handles the mobility management operations. Not shown are the Operations
A GSM network is composed of several functional entities, whose functions and interfaces are specified. Figure 1 shows the layout of a generic GSM network. The GSM network can be divided into three broad parts.  Subscriber carries the Mobile Station. The Base Station Subsystem controls the radio link with the Mobile Station. The Network Subsystem, the main part of which is the Mobile services Switching Center (MSC), performs the switching of calls between the mobile users, and between mobile and fixed network users. The MSC also handles the mobility management operations. Not shown is the Operations intendance Center, which oversees the proper operation and setup of the network. The Mobile Station and the Base Station Subsystem communicate across the Um interface, also known as the air interface or radio link. The Base Station Subsystem communicates with the Mobile services Switching Center across the A interface. 
 4.7.6.1 Mobile Station:
The mobile station (MS) consists of the mobile equipment (the terminal) and a smart card called the Subscriber Identity Module (SIM). The SIM provides personal mobility, so that the user can have access to subscribed services irrespective of a specific terminal. By inserting the SIM card into another GSM terminal, the user is able to receive calls at that terminal, make calls from that terminal, and receive other subscribed services.
The mobile equipment is uniquely identified by the International Mobile Equipment Identity (IMEI). The SIM card contains the International Mobile Subscriber Identity (IMSI) used to identify the subscriber to the system, a secret key for authentication, and other information. The IMEI and the IMSI are independent, thereby allowing personal mobility. The SIM card may be protected against unauthorized use by a password or personal identity number.
4.7.6.2 Base Station Subsystem:
The Base Station Subsystem is composed of two parts, the Base Transceiver Station (BTS) and the Base Station Controller (BSC). These communicate across the standardized Abis interface, allowing (as in the rest of the system) operation between components made by different suppliers.
The Base Transceiver Station houses the radio transceivers that define a cell and handles the radio-link protocols with the Mobile Station. In a large urban area, there will potentially be a large number of BTSs deployed, thus the requirements for a BTS are ruggedness, reliability, portability, and minimum cost.
The Base Station Controller manages the radio resources for one or more BTSs. It handles radio-channel setup, frequency hopping, and handovers, as described below. The BSC is the connection between the mobile station and the Mobile service Switching Center (MSC).

4.7.6.3 Network Subsystem

The central component of the Network Subsystem is the Mobile services Switching Center (MSC). It acts like a normal switching node of the PSTN or ISDN, and additionally provides all the functionality needed to handle a mobile subscriber, such as registration, authentication, location updating, handovers, and call routing to a roaming subscriber. These services are provided in conjunction with several functional entities, which together form the Network Subsystem. The MSC provides the connection to the fixed networks (such as the PSTN or ISDN). Signaling between functional entities in the Network Subsystem uses Signaling System Number 7 (SS7), used for trunk signaling in ISDN and widely used in current public networks.
The Home Location Register (HLR) and Visitor Location Register (VLR), together with the MSC, provide the call-routing and roaming capabilities of GSM. The HLR contains all the administrative information of each subscriber registered in the corresponding GSM network, along with the current location of the mobile. The location of the mobile is typically in the form of the signaling address of the VLR associated with the mobile as a distributed database. station. The actual routing procedure will be described later. There is logically one HLR per GSM network, although it may be implemented
The Visitor Location Register (VLR) contains selected administrative information from the HLR, necessary for call control and provision of the subscribed services, for each mobile currently located in the geographical area controlled by the VLR. Although each functional entity can be implemented as an independent unit, all manufacturers of switching equipment to date implement the VLR together with the MSC, so that the geographical area controlled by the MSC corresponds to that controlled by the VLR, thus simplifying the signalling required. Note that the MSC contains no information about particular mobile stations --- this information is stored in the location registers.
The other two registers are used for authentication and security purposes. The Equipment Identity Register (EIR) is a database that contains a list of all valid mobile equipment on the network, where each mobile station is identified by its International Mobile Equipment Identity (IMEI). An IMEI is marked as invalid if it has been reported stolen or is not type approved. The Authentication Center (AuC) is a protected database that stores a copy of the secret key stored in each subscriber's SIM card, which is used for authentication and encryption over the radio channel.
4.8 LIQUID CRYSTAL DISPLAY:
Liquid crystal displays (LCDs) have materials, which combine the properties of both liquids and crystals. Rather than having a melting point, they have a temperature range within which the molecules are almost as mobile as they would be in a liquid, but are grouped together in an ordered form similar to a crystal. An LCD consists of two glass panels, with the liquid crystal material sand witched in between them. The inner surface of the glass plates are coated with transparent electrodes which define the character, symbols or patterns to be displayed polymeric layers are present in between the electrodes and the liquid crystal, which makes the liquid crystal molecules to maintain a defined orientation angle. One each polarisers are pasted outside the two glass panels. These polarisers would rotate the light rays passing through them to a definite angle, in a particular direction. When the LCD is in the off state, light rays are rotated by the two polarisers and the liquid crystal, such that the light rays come out of the LCD without any orientation, and hence the LCD appears transparent.
When sufficient voltage is applied to the electrodes, the liquid crystal molecules would be aligned in a specific direction. The light rays passing through the LCD would be rotated by the polarisers, which would result in activating/ highlighting the desired characters. The LCD’s are lightweight with only a few millimeters thickness. Since the LCD’s consume less power, they are compatible with low power electronic circuits, and can be powered for long durations. The LCD’s don’t generate light and so light is needed to read the display. By using backlighting, reading is possible in the dark. The LCD’s have long life and a wide operating temperature range. Changing the display size or the layout size is relatively simple which makes the LCD’s more customers friendly.

4.8.1 LCD operation:

    1. In recent years the LCD is finding widespread use replacing LEDs(seven-segment LEDs  or other multisegment LEDs).This is due to the following reasons:
  1. The declining prices of LCDs.
  2. The ability to display numbers, characters and graphics. This is in                            contract to LEDs, which are  limited to numbers and a few characters.
  3. Incorporation of a refreshing controller into the LCD, there by          
  4. relieving the CPU of the task of refreshing the LCD. In the contrast,  
  5. the LED must be refreshed by the CPU to keep  displaying the data.
  6. Ease of programming for characters and graphics.
 16X2 LCD:

 PIN DESCRIPTION OF LCD:
RS: REGISTER SELECT:
Ø    there are two registers inside the LCD.
Ø    Command Register and Data Register.
Ø    RS pin is used for their selection.
·                  if RS=0, command register is selected.
·                  if RS=1, data register is selected.
R/W: READ/WRITE
§     Allows user to read the information from the LCD and write the information to the LCD.
            R/W=1 when reading
            R/W=0, when writing
E: ENABLE
§    used by the LCD to latch the information from its data lines.
§    a high to low pulse must be applied to this pin to receive data.
§    this pulse must be 450ns wide.
VCC: +5V POWER SUPPLY
VSS: GROUND
VEE: TO CONTROL LCD CONTRAST.
D0-D7:            8 Bit data pins used to send information to the LCD or read the contents of the LCD’s internal registers.
LCD COMMANDS:

0x38: 2 lines and 5x7 matrix
0x01: clear display screen
0x0E: display on, cursor blinking
0x06: increment cursor(shift cursor to right)
0x80: force cursor to beginning of 1st line
0xC0:  force cursor to beginning of 2nd line
ALGORITHM TO SEND DATA TO LCD:
              1.Make R/W low
              2.Make RS=0 ;if data byte is command
      RS=1 ;if data byte is data (ASCII value)
          3.Place data byte on data register
          4.Pulse E (HIGH to LOW)
          5.Repeat the steps to send another data byte
4.9 ignition switch:
The term ignition switch is often used interchangeably to refer to two very different parts. The lock cylinder into which the key is inserted, and the electronic switch that sits just behind the lock cylinder. In some cars, these two parts are combined into one unit, but in other cars they remain separate. It is advisable to check your car's shop manual before attempting to purchase an ignition switch, to ensure that you buy the correct part.
In order to start a car, the engine must be turning. Therefore, in the days before ignition switches, car engines had to be turned with a crank on the front of the car in order to start them. The starter performs this same operation by turning the engine's flywheel, a large, flat disc with teeth on the outer edge. The starter has a gear that engages these teeth when it is powered, rapidly and briefly turning the flywheel, and thus the engine.
The ignition switch generally has four positions: off, accessories, on, and start. Some cars have two off positions, off and lock; one turns off the car, and the other allows the key to be removed from the ignition. When the key is turned to the accessories position, certain accessories, such as the radio, are powered; however, accessories that use too much battery power, such as window motors, remain off in order to prevent the car's battery from being drained. The accessories position uses the least amount of battery power when the engine is not running, which is why drive-in movie theaters recommend that the car be left in the accessories mode during the movie.
The on position turns on all of the car's systems, including systems such as the fuel pump, because this is the position the ignition switch remains in while the car's engine is running. The start position is spring loaded so that the ignition switch will not remain there when the key is released. When the key is inserted into the ignition switch lock cylinder and turned to the start position, the starter engages; when the key is released, it returns to the on position, cutting power to the starter. This is because the engine runs at speeds that the starter cannot match, meaning that the starter gear must be retracted once the engine is running on its own.
Either the ignition switch or the lock cylinder may fail in a car, but both circumstances have very different symptoms. When the ignition switch fails, generally the electrical wiring or the plastic housing develops problems. The car may not turn on and/or start when this happens. Also, the spring-loaded start position could malfunction, in which case the starter will not engage unless the key is manually turned back to the on position.
When the lock cylinder malfunctions, however, the operation of the key itself will become problematic. If the tumblers become stripped, the lock cylinder may be able to turn with any key, or you may be able to remove the key when the car is on. If the tumblers begin to shift, the lock cylinder may not turn. Sometimes the key can be wiggled until the lock cylinder turns, but it is important to remember that this is only a temporary fix
4.10 MAX-232:
The MAX232 from Maxim was the first IC which in one package contains the necessary drivers (two) and receivers (also two), to adapt the RS-232 signal voltage levels to TTL logic. It became popular, because it just needs one voltage (+5V) and generates the necessary RS-232 voltage levels (approx. -10V and +10V) internally. This greatly simplified the design of circuitry. Circuitry designers no longer need to design and build a power supply with three voltages (e.g. -12V, +5V, and +12V), but could just provide one +5V power supply, e.g. with the help of a simple 78x05 voltage converter.
The MAX232 has a successor, the MAX232A. The ICs are almost identical, however, the MAX232A is much more often used (and easier to get) than the original MAX232, and the MAX232A only needs external capacitors 1/10th the capacity of what the original MAX232 needs.
It should be noted that the MAX 232 is just a driver/receiver. It does not generate the necessary RS-232 sequence of marks and spaces with the right timing, it does not decode the RS-232 signal, it does not provide a serial/parallel conversion. All it does is to convert signal voltage levels. Generating serial data with the right timing and decoding serial data has to be done by additional circuitry, e.g. by a 16550 UART or one of these small micro controllers (e.g. Atmel AVR, Microchip PIC) getting more and more popular.
The MAX232 and MAX232A were once rather expensive ICs, but today they are cheap. It has also helped that many companies now produce clones (ie. Sipex). These clones sometimes need different external circuitry, e.g. the capacities of the external capacitors vary. It is recommended to check the data sheet of the particular manufacturer of an IC instead of relying on Maxim's original data sheet.
The original manufacturer (and now some clone manufacturers, too) offers a large series of similar ICs, with different numbers of receivers and drivers, voltages, built-in or external capacitors, etc. E.g. The MAX232 and MAX232A need external capacitors for the internal voltage pump, while the MAX233 has these capacitors built-in. The MAX233 is also between three and ten times more expensive in electronic shops than the MAX232A because of its internal capacitors. It is also more difficult to get the MAX233 than the garden variety MAX232A.

4.10.1 A Typical Application

The MAX 232(A) has two receivers (converts from RS-232 to TTL voltage levels) and two drivers (converts from TTL logic to RS-232 voltage levels). This means only two of the RS-232 signals can be converted in each direction. The old MC1488/1498 combo provided four drivers and receivers.
Typically a pair of a driver/receiver of the MAX232 is used for
·                     TX and RX
And the second one for
·                     CTS and RTS.
There are not enough drivers/receivers in the MAX232 to also connect the DTR, DSR, and DCD signals. Usually these signals can be omitted when e.g. communicating with a PC's serial interface. If the DTE really requires these signals either a second MAX232 is needed, or some other IC from the MAX232 family can be used (if it can be found in consumer electronic shops at all). An alternative for DTR/DSR is also given below.
Maxim's data sheet explains the MAX232 family in great detail, including the pin configuration and how to connect such an IC to external circuitry. This information can be used as-is in own design to get a working RS-232 interface. Maxim's data just misses one critical piece of information: How exactly to connect the RS-232 signals to the IC. So here is one possible example:
In addition one can directly wire DTR (DB9 pin 4) to DSR (DB9 pin 6) without going through any circuitry. This gives automatic (brain dead) DSR acknowledgment of an incoming DTRsignal.
Sometimes pin 6 of the MAX232 is hard wired to DCD (DB9 pin 1). This is not recommended. Pin 6 is the raw output of the voltage pump and inverter for the -10V voltage. Drawing currents from the pin leads to a rapid breakdown of the voltage, and as a consequence to a breakdown of the output voltage of the two RS-232 drivers. It is better to use software which doesn't care about DCD, but does hardware-handshaking via CTS/RTS only.
The circuitry is completed by connecting five capacitors to the IC as it follows. The MAX232 needs 1.0µF capacitors, the MAX232A needs 0.1µF capacitors. MAX232 clones show similar differences. It is recommended to consult the corresponding data sheet. At least 16V capacitor types should be used. If electrolytic or tantalic capacitors are used, the polarity has to be observed. The first pin as listed in the following table is always where the plus pole of the capacitor should be connected to.
The 5V power supply is connected to
·                     +5V: Pin 16
·                     GND: Pin 15
The MAX232 is a dual driver/receiver that includes a capacitive voltage generator to supply EIA-232 voltage levels from a single 5-V supply. Each receiver converts EIA-232 inputs to 5-V TTL/CMOS levels. These receivers have a typical threshold of 1.3 V and a typical hysteresis of 0.5 V, and can accept 30-V inputs. Each driver converts TTL/CMOS input levels into EIA-232 levels. The driver, receiver, and voltage-generator functions are available as cells in the Texas Instruments Lin ASIClibrary.
4.11  DC Motor :
DC motors are configured in many types and sizes, including brush less, servo, and gear motor types. A motor consists of a rotor and a permanent magnetic field stator. The magnetic field is maintained using either permanent magnets or electromagnetic windings. DC motors are most commonly used in variable speed and torque.
           Motion and controls cover a wide range of components that in some way are used to generate and/or control motion. Areas within this category include bearings and bushings, clutches and brakes, controls and drives, drive components, encoders and resolves, Integrated motion control, limit switches, linear actuators, linear and rotary motion components, linear position sensing, motors (both AC and DC motors), orientation position sensing, pneumatics and pneumatic components, positioning stages, slides and guides, power transmission (mechanical), seals, slip rings, solenoids and springs. Motors are the devices that provide the actual speed and torque in a drive system.  This family includes AC motor types (single and multiphase motors, universal, servo motors, induction, synchronous, and gear motor) and DC motors (brush less, servo motor, and gear motor) as well as linear, stepper and air motors, and motor contactors and starters.
In any electric motor, operation is based on simple electromagnetism. A current-carrying conductor generates a magnetic field; when this is then placed in an external magnetic field, it will experience a force proportional to the current in the conductor, and to the strength of the external magnetic field. As you are well aware of from playing with magnets as a kid, opposite (North and South) polarities attract, while like polarities (North and North, South and South) repel. The internal configuration of a DC motor is designed to harness the magnetic interaction between a current-carrying conductor and an external magnetic field to generate rotational motion.
Let's start by looking at a simple 2-pole DC electric motor (here red represents a magnet or winding with a "North" polarization, while green represents a magnet or winding with a "South" polarization).
Figure 27: Block Diagram of the DC motor
Every DC motor has six basic parts -- axle, rotor (a.k.a., armature), stator, commutator, field magnet(s), and brushes. In most common DC motors (and all that Beamers will see), the external magnetic field is produced by high-strength permanent magnets1. The stator is the stationary part of the motor -- this includes the motor casing, as well as two or more permanent magnet pole pieces. The rotor (together with the axle and attached commutator) rotates with respect to the stator. The rotor consists of windings (generally on a core), the windings being electrically connected to the commutator. The above diagram shows a common motor layout -- with the rotor inside the stator (field) magnets.
The geometry of the brushes, commutator contacts, and rotor windings are such that when power is applied, the polarities of the energized winding and the stator magnet(s) are misaligned, and the rotor will rotate until it is almost aligned with the stator's field magnets. As the rotor reaches alignment, the brushes move to the next commutator contacts, and energize the next winding. Given our example two-pole motor, the rotation reverses the direction of current through the rotor winding, leading to a "flip" of the rotor's magnetic field, and driving it to continue rotating.
In real life, though, DC motors will always have more than two poles (three is a very common number). In particular, this avoids "dead spots" in the commutator. You can imagine how with our example two-pole motor, if the rotor is exactly at the middle of its rotation (perfectly aligned with the field magnets), it will get "stuck" there. Meanwhile, with a two-pole motor, there is a moment where the commutator shorts out the power supply (i.e., both brushes touch both commutator contacts simultaneously). This would be bad for the power supply, waste energy, and damage motor components as well. Yet another disadvantage of such a simple motor is that it would exhibit a high amount of torque” ripple" (the amount of torque it could produce is cyclic with the position of the rotor).
                                               
Figure 28: Block Diagram of the DC motor having two poles only

Figure 29: Block Diagram of the DC motor having Three poles
You'll notice a few things from this -- namely, one pole is fully energized at a time (but two others are "partially" energized). As each brush transitions from one commutator contact to the next, one coil's field will rapidly collapse, as the next coil's field will rapidly charge up (this occurs within a few microsecond). We'll see more about the effects of this later, but in the meantime you can see that this is a direct result of the coil windings' series wiring:
Figure 30: Internal Block Diagram of the Three pole DC motor
There's probably no better way to see how an average dc motor is put together, than by just opening one up. Unfortunately this is tedious work, as well as requiring the destruction of a perfectly good motor.  This is a basic 3-pole dc motor, with 2 brushes and three commutator contacts.
4.12 H-BRIDGE:
Figure 31: H-Bridge
DC motors are typically controlled by using a transistor configuration called an "H-bridge". This consists of a minimum of four mechanical or solid-state switches, such as two NPN and two PNP transistors. One NPN and one PNP transistor are activated at a time. Both NPN and PNP transistors can be activated to cause a short across the motor terminals, which can be useful for slowing down the motor from the back EMF it creates.

4.12.1 Basic Theory

H-bridge. Sometimes called a "full bridge" the H-bridge is so named because it has four switching elements at the "corners" of the H and the motor forms the cross bar.
The key fact to note is that there are, in theory, four switching elements within the bridge. These four elements are often called, high side left, high side right, low side right, and low side left (when traversing in clockwise order).
The switches are turned on in pairs, either high left and lower right, or lower left and high right, but never both switches on the same "side" of the bridge. If both switches on one side of a bridge are turned on it creates a short circuit between the battery plus and battery minus terminals. If the bridge is sufficiently powerful it will absorb that load and your batteries will simply drain quickly. Usually however the switches in question melt.
To power the motor, you turn on two switches that are diagonally opposed. In the picture to the right, imagine that the high side left and low side right switches are turned on.
The current flows and the motor begins to turn in a "positive" direction. Turn on the high side right and low side left switches, then Current flows the other direction through the motor and the motor turns in the opposite direction.
One more topic in the basic theory section, quadrants. If each switch can be controlled independently then you can do some interesting things with the bridge, some folks call such a bridge a "four quadrant device" (4QD get it?). If you built it out of a single DPDT relay, you can really only control forward or reverse. You can build a small truth table that tells you for each of the switch's states, what the bridge will do. As each switch has one of two states, and there are four switches, there are 16 possible states. However, since any state that turns both switches on one side on is "bad" (smoke issues forth: P), there are in fact only four useful states (the four quadrants) where the transistors are turned on.
High Side Left
High Side Right
Low Side Left
Low Side Right
Quadrant Description
On
Off
Off
On
Forward Running
Off
On
On
Off
Backward Running
On
On
Off
Off
Braking
Off
Off
On
On
Braking
Table 9: H-Bridge truth table
The last two rows describe a maneuver where you "short circuit" the motor which causes the motors generator effect to work against itself. The turning motor generates a voltage which tries to force the motor to turn the opposite direction. This causes the motor to rapidly stop spinning and is called "braking" on a lot of H-bridge designs. Of course there is also the state where all the transistors are turned off. In this case the motor coasts freely if it was spinning and does nothing if it was doing nothing.
4.12.2     Motor Driver Connections:
The motor driver requires 2 control inputs for each motor. Since we drive 2 motors, we need 4 controls
Figure 32: Motor Driver Connections
Inputs from the microcontroller. Since it has many pins which can be configured as outputs, there are many options for implementation. For example, in our robot the last 4 bits of Port B (RB4, RB5, RB6,RB7 - Pins 37 to 40) are used to control the rotation direction of the motors . The enable pins of the motor driver are connected to the PWM outputs of the microcontroller (Pins 16and 17). This is because, as was mentioned above, by changing the width of the pulse (implying changing the enable time of the driver) one can change the speed of the motor. The truth table for motor driver is as shown in Table 10, where H = high, L = low, and Z =high output impedance state.
THE TRUTH TABLE OF THE MOTOR DRIVER
Input
Enable
output
H
H
H
L
H
L
H
L
z
L
L
z
Table 10: Truth table of the motor driver
DRIVER CONTROL INPUTS
Direction
Input 1
Input 2
Input 3
Input 4
Forward
H
L
L
H
Backward
L
H
H
L
Table 11: Driver control inputs
Since the motors are reverse aligned, in order to have the robot Move forward they must be configured such that one of them turns forward and the other one turns backward. In case of any requirement for the robot to move backward, it is sufficient to just reverse the outputs of the control pins. For example, in our robot while moving forward, inputs of the motor driver have states shown in the first row Of Table 11, whereas for backward movement, the states shown in the second row of Table 11 is applied.




chapter 5
ImplEmentation of interfacing design
5.1 Introduction:
Microcontrollers are useful to the extent that they communicate with other devices, such as sensors, motors, switches, keypads, displays, memory and even other micro-controllers. Many interface methods have been developed over the years to solve the complex problem of balancing circuit design criteria such as features, cost, size, weight, power consumption. Many microcontroller designs typically mix multiple interfacing methods. In a very simplistic form, a micro-controller system can be viewed as a system that reads from (monitors) inputs, performs processing and writes to (controls) outputs. Here I am using few interfacing techniques for design of Fingerprint protected anti theft tracking system. Here I am using two UART ports for interfacing Fingerprint, GPS and GSM modules using a latch. Remaining motor, vibration sensor, stop switch, enrolling switch etc are directly connected to GPIO pins.
5.2 Schematic Diagram:
5.3 Schematic Explanatio
5.3.1 GPS connections:
Pins                  connections
1.                    VCC (+5v)
2.                    This pin is connected to the T1OUT of the MAX -232 IC
3.                    This pin is connected to the R1IN of the MAX -232 IC
4.                    GND
5.                    GND
5.3.2 GSM connections:
Pins                  connections
1.                     VCC (+5v)
2.                      This pin is connected to the T2OUT of the MAX -232 IC
3.                     This pin is connected to the R2IN of the MAX -232 IC
4.                     GND
5.                     GND

5.3.3 MAX-232 connections to microcontroller in is made by using a latch in between MAX-232 and microcontroller:
Pins                 connections
11                    This pin is connected to P0.0 /TXD0/PWM1 of the Micro controller
12                    This pin is connected to P0.1 /RXD0/PWM3/EINT0
13                    This pin is connected to P0.2/SCL0/CAP0.0
14                    This pin is connected to P0.3/SDA0/MAT0.0/EINT1
15                    Ground
16                    vcc
5.3.4 LCD connections to Micro controller:
Pins                 Connections
1                      VSS (ground)
2                      VCC (+5V)
3                      10k pot
4                      this pin is connected to P1.16 of the micro controller
6                      R/w, this pin is connected to P1.17 of the micro controller
11-14               these pins are connected through P1.18 to P1.21 of the micro controller
15                     this pin is connected to VCC
16                     this pin is connected to GND
5.3.5 Fingerprint connections to the microcontroller:
Pins                 Connections
VCC                VCC_BAR
RX                  P0.8/TXD1/PWM4/AD1.1
TX                   P0.9/RXD1/PWM6/EINT3
GND               GND
IR Sensor is connected to P1.31/TRST
Vibration sensor is connected to P1.30/TMS
DC motor is connected to P1.29/TCK


















CHAPTER 6
RESULTS

          6.1 After pressing the reset switch


6.2 While login on fingerprint


1.3While vibration sensor activated
6.4 Enrolling process output
6.5 While sending LOCATION message

  



6.6 While sending stop message








CONCLUSION:
I strongly believe that the development of a nation could be done only through progressive development of all class of people. Hence this vehicle tracking system which not only proves to be effective but also cheap, would definitely help a great deal in bringing down expenses ,ensuring the safety of the vehicle be it 2 or 3 or 4 or even higher wheeled vehicles.
FUTURE SCOPE:
This system can be developed for car security systems. This a type of biometric security system gives more security among all other biometrics. This can be further developed for ATM centers for authentication. This can be developed for door locking and unlocking security systems. This can be developed for authentication of any other electronic machine.















REFERENCES:
[1].   Ganesh, Balaji, Varadhan “Anti-Theft Tracking System for Automobiles” 2011  IEEE Paper
[2].  Islam,  Karhu, Salonen” GPS and GSM antenna with a capacitive feed for a personal        avigator device”-IEEE Paper 2010
[3]. Cai-Cong Wu, Xiu-Wan Chen, Hong Li, Zhong-Zhong Wu, Ying-Chun Tao”Design and development of farm vehicle monitoring and intelligent dispatching system” 2004 IEEE paper.
[4]. Qiang Liu; Huapu Lu; Hongliang Zhang; Bo Zou “Research and Desing of Intelligent Vehicle Monitoring System Based on GPS/GSM” 2006 IEEE Paper.
[5]. Hindawi, Nader “Performance of differential GPS based on a real-time algorithm using SMS services of GSM network”  2012 IEEE Paper.
[6]. Peng Chen; Shuang Liu “Intelligent Vehicle Monitoring System, Based on GPS, GSM and GIS”  2010 IEEE Paper.
[7]. Kaveh Pahlavan and Prashanth Krishnamurthy, Principles of wireless networks: A unified                                              approach 1st,” Prentice Hall PTR Upper Saddle River, NJ, USA.2001.
[8].  datasheetarchive.com- For ARM7TDMI-S.
[9]. arm.com- For ARM
[10].         beginnersguide.com - For GSM.
[11].         howstuffworks.com- For GSM.
[12].         rajguruelectronics.com-Fingerprint

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